RTL Engineer

Capgemini; Odivelas; Híbrido; EUR 55 000 - 75 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health insurance

Life insurance

Hybrid work model

Career growth programs

Training and certifications

Resumo da oferta

Capgemini Engineering in Portugal is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out. You will define microarchitectures for complex SoCs, implement RTL in Verilog/SystemVerilog/VHDL, and collaborate across Verification, Synthesis, STA, and DFT teams.

The role emphasizes timing closure, low-power techniques, and automation scripting, with a hybrid work model and opportunities across national and international projects.

Qualificações

• Bachelor’s or Master’s in Electrical or Computer Engineering or related field.
• 6+ years in RTL/ASIC/SoC/VLSI design.
• Strong Verilog, SystemVerilog and/or VHDL knowledge.
• Experience with microarchitecture definition and complex digital design.
• Knowledge of SoC methodologies and integration.
• Experience with Lint, CDC, and Low Power methodologies.
• Solid synthesis and STA understanding.
• Familiarity with ARM/RISC-V/x86 CPU architectures.
• Proficiency in Python or similar scripting languages.

Responsabilidades

• Perform feasibility studies to support system architecture and interface specs.
• Define and develop microarchitectures for complex digital blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Execute RTL quality checks, including Lint, CDC, and Low Power verification.
• Develop timing constraints and support synthesis and timing closure activities.
• Collaborate with Verification, Synthesis, STA, Physical Design, and DFT teams.
• Support design bring-up, integration and tape-out activities.
• Create automation scripts and design flows to improve efficiency.
• Participate in technical reviews and continuous improvement initiatives.

Conhecimentos

RTL design

ASIC/SoC

Verilog/SystemVerilog

VHDL

Synthesis

Static Timing Analysis

Lint/CDC

Low Power design

CPU architectures (ARM/RISC-V/x86)

Python scripting

Formação académica

Bachelor’s or Master’s in Electrical or Computer Engineering

Ferramentas

Python

Descrição da oferta de emprego

CAPGEMINI ENGINEERING

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

YOUR ROLE

As a Senior RTL Engineer, you will be responsible for driving digital design activities from architecture definition through tape-out, ensuring the successful delivery of high-performance and power-efficient products. In this role, you will:

• Perform feasibility studies to support system architecture definition, requirements analysis, and interface specification.
• Define and develop microarchitectures for complex digital blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Execute RTL quality checks, including Lint, CDC, and Low Power verification.
• Develop timing constraints and support synthesis and timing closure activities.
• Collaborate closely with Verification, Synthesis, STA, Physical Design, and DFT teams to achieve functionality, performance, power, and area targets.
• Support design bring-up, integration, and tape-out activities.
• Create and maintain automation scripts, design flows, and engineering tools to improve development efficiency.
• Participate in technical reviews and contribute to continuous improvement initiatives.

YOUR PROFILE

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of experience in RTL, ASIC, SoC, or VLSI design.
• Strong knowledge of Verilog, SystemVerilog, and/or VHDL.
• Proven experience in microarchitecture definition and complex digital design development.
• Solid understanding of SoC design methodologies and integration.
• Hands-on experience with Lint, CDC, and Low Power design methodologies.
• Good knowledge of synthesis flows and Static Timing Analysis (STA).
• Familiarity with CPU architectures and instruction sets such as ARM, RISC-V, or x86.
• Experience with scripting and programming languages such as Python, Perl, or C.
• Understanding of verification methodologies and design flows.
• Strong problem-solving skills and attention to detail.
• Excellent communication skills and ability to work effectively in multicultural and multidisciplinary environments.

WHAT YOU’LL LOVE ABOUT WORKING HERE

• Join a multicultural and inclusive team environment.
• Enjoy a supportive atmosphere promoting work life balance.
• Hybrid work.
• Your career growth is central to our mission.
• Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.
• Access valuable training and certifications in cutting edge technologies.
• Engage in exciting national and international projects.
• Health and life insurance.
• Referral program with bonuses for talent recommendations.
• Great office locations.

ABOUT CAPGEMINI

Capgemini is an AI-powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people. With our strong heritage of nearly 60 years, we are a responsible and diverse group of 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering and business operations.