Research Grant in Formal Verification for HLS Hardware

Inesc Tec; Portugal; On-site; EUR 11,000 - 13,000; Full time

Benefits offered by this job

Health insurance

Job summary

INESC TEC in Portugal is inviting applications for a 6-month Research Grant (BI) within the scope of the Multiannual Funding of R&D Units 2025-2029. The grant focuses on formal verification techniques for high-level synthesis (HLS) and the verification of HDL designs translated from C/C++ descriptions.

The ideal candidate will study HLS tools, review state-of-the-art verification methods, and develop an automated approach for HDL verification.

Qualifications

• BSc in computer science or related field.
• Average BSc and MSc grades of at least 15.
• Experience with model checking tools.
• Experience with deductive verification tools.
• Preference for knowledge in language processing and formal semantics.

Responsibilities

• Investigate formal verification techniques for validating high-level synthesis (HLS) approaches for hardware design.
• Study existing HLS techniques and tools for C/C++ to HDL translation.
• Propose and design an automated approach for formal verification of HDL designs generated through HLS.

Skills

Model checking

Deductive verification

Language processing

Formal semantics

Education

BSc in Computer Science

MSc in related area

Tools

Model checking tools

Deductive verification tools

Job description

INESC TEC in Portugal is inviting applications for a 6-month Research Grant (BI) within the scope of the Multiannual Funding of R&D Units 2025-2029. The grant focuses on formal verification techniques for high-level synthesis (HLS) and the verification of HDL designs translated from C/C++ descriptions.

The ideal candidate will study HLS tools, review state-of-the-art verification methods, and develop an automated approach for HDL verification.