Analog IC Layout Engineer – FinFET Technologies

ADVANS Group; Lisboa; On-site; EUR 65,000 - 85,000; Full time

Benefits offered by this job

Health insurance

Professional development opportunities

Integration program in a professional, young & dynamic team

Competitive salaries & benefits

International work environment

Job summary

ADVANS Group in Portugal is searching for experienced Analog IC Layout Engineers to join their team in Lisbon. The role involves designing and implementing analog IC layouts, performing placement and routing, and ensuring reliability in FinFET technologies.

The ideal candidate will have a BSc or MSc in Electrical Engineering, strong experience with Cadence tools, and excellent English communication skills. The position offers a dynamic work environment with competitive salaries and health insurance.

Qualifications

• 5+ years of professional experience in Analog IC Layout, with at least 2 years in FinFET technologies.
• Hands-on experience with Cadence Virtuoso, Assura, PVS, and/or Mentor Calibre layout tools.
• Excellent English communication skills, both written and verbal.

Responsibilities

• Design and implement analog IC layouts including floor planning and integration.
• Perform placement and routing at block, top, and full-chip levels.
• Execute and debug physical verification checks using industry-standard tools.

Skills

Analog Layout Principles

Cadence Virtuoso

Scripting Knowledge (SKILL, Shell, Perl, TCL)

FinFET Technologies (7nm, 5nm, 3nm)

Education

BSc or MSc in Electrical Engineering

Tools

Assura

PVS

Mentor Calibre

Job description

Overview

ADVANS Group in Portugal is looking for experienced Analoc IC Layout Engineers to work in the semiconductor industry in our new Lisbon offices.

Responsibilities

• Design and implement analog IC layouts including floor planning, integration, area estimation, and abstract view generation


• Perform placement and routing at block, top, and full-chip levels in the Cadence Virtuoso environment


• Develop and layout I/O structures, ESD protection, PADs, and seal rings following advanced node constraints


• Execute and debug physical verification checks including DRC, LVS, ERC, and antenna rule checks using industry-standard tools (Assura, PVS, Calibre)


• Conduct parasitic and electromigration (EM) extractions, and collaborate closely with Analog Design Engineers to ensure performance and reliability


• Address and optimize FinFET-specific challenges, including layout-dependent effects (LDE), double-patterning, DFM, and reliability constraints in nodes below 10nm

Qualifications

• BSc or MSc in electrical engineering or related field


• 5+ years of professional experience in Analog IC Layout, with at least 2 years in FinFET technologies (e.g., 7nm, 5nm, 3nm nodes)


• Hands-on experience with Cadence Virtuoso, Assura, PVS, and/or Mentor Calibre layout and verification tools


• Strong understanding of analog layout principles, ESD/LU protection, parasitic-aware design, DFM, EM, antenna effects, and FinFET-specific LDE


• Comfortable working in a Linux-based CAD environment


• Scripting knowledge (e.g., SKILL, Shell, Perl, TCL) is a plus


• Excellent English communication skills, both written and verbal

Benefits

• Integration program in a professional, young & dynamic team


• Professional development opportunities


• Competitive salaries & benefits


• Health insurance


• International work environment