DSP Architect

Mulya Technologies; Lisboa; Presencial; EUR 70 000 - 90 000; Tempo integral

Resumo da oferta

Mulya Technologies is seeking a highly skilled DSP Architect with over 10 years of experience in DSP algorithms for SerDes. The position involves developing and optimizing DSP algorithms for high-speed serial links such as Ethernet, PCIe, and UCIe.

The ideal candidate will have a strong background in FPGA prototyping, silicon bring-up, and a degree in Electrical/Electronics Engineering. This role offers the opportunity to work on cutting-edge technology in a dynamic environment.

Qualificações

• 10+ years in DSP algorithm development for SerDes PHYs.
• Strong background in DSP algorithms and FPGA prototyping.
• Education in Electrical/Electronics Engineering with a specialization in Signal processing.

Responsabilidades

• Develop and optimize DSP algorithms for SerDes PHYs (Ethernet/PCIe/UCIe).
• Prototype DSP blocks on FPGA platforms for pre-silicon validation.
• Perform lab debug and silicon characterization of high-speed links.
• Collaborate with analog/mixed-signal teams on CDR, PLL/DLL, equalization schemes.
• Document workflows and support IP integration into customer SoCs.

Conhecimentos

DSP Algorithms for SerDes

Equalization (FFE/DFE), echo cancellation, adaptive filtering, CDR loops

Ethernet, PCIe, UCIe high-speed serial links

Channel modelling, jitter/noise analysis, BER optimization

RTL design and verification

FPGA prototyping

Silicon bring-up, validation, correlation with simulation models

Analytical problem-solving

Cross-functional collaboration

Clear technical communication

Formação académica

B.E./M.Tech in Electrical/Electronics Engineering

Ferramentas

MATLAB

Python

FPGA toolchains

Cadence digital tools

Xilinx Vivado

Intel Quartus

Descrição da oferta de emprego

We are a leading provider of high-performance, ultra-low power IP cores optimized for advanced semiconductor nodes, enabling the development of cutting-edge systems-on-chip (SoCs) for applications such as 5G, AI, LiDAR, radar, networking, and IoT. Known for its innovative small geometry solutions, our expertise encompasses data converter IP cores ranging from 6-bit to 14-bit resolutions and sampling rates up to over 20 Gsps.

Apart from the above we need 10+ year DSP engineers with Serdes background.

DSP Architect (10+ Years)

Core Expertise

• DSP Algorithms for SerDes:
• Deep knowledge of equalization (FFE/DFE), echo cancellation, adaptive filtering, CDR loops.
• Experience across Ethernet, PCIe, UCIe high-speed serial links.
• Skilled in channel modelling, jitter/noise analysis, BER optimization.
• Digital RTL & FPGA Prototyping:
• Strong background in RTL design and verification using Cadence digital tools (Knowledge wrt Genus for synthesis, Innovus for P&R, JasperGold for formal verification).
• Hands‑on FPGA prototyping of SerDes DSP blocks (Xilinx Vivado, Intel Quartus).
• Implemented training sequence debug, retimer logic, and sideband channel handling on FPGA platforms.
• Bench expertise with oscilloscopes, BERTs and high-speed probes.
• Experience in silicon bring‑up, validation, and correlation with simulation models.

Qualifications

• Education: B.E./M.Tech in Electrical/Electronics Engineering (Signal processing specialization).
• Experience: 10+ years in DSP algorithm development for SerDes PHYs.
• Tools & Languages:
• MATLAB, Python (algorithm modeling, post-processing).
• FPGA toolchains.
• Soft Skills: Analytical problem-solving, cross‑functional collaboration, clear technical communication.

Responsibilities

• Develop and optimize DSP algorithms for SerDes PHYs (Ethernet/PCIe/UCIe).
• Prototype DSP blocks on FPGA platforms for pre‑silicon validation.
• Perform lab debug and silicon characterization of high‑speed links.
• Collaborate with analog/mixed‑signal teams on CDR, PLL/DLL, equalization schemes.
• Document workflows and support IP integration into customer SoCs.