FPGA Engineer – radio VDES

LusoSpace Lda; Porto; Presencial; EUR 40 000 - 60 000; Tempo integral

Resumo da oferta

LusoSpace Lda is looking for a Senior FPGA Engineer in Porto, Portugal, responsible for developing a VHF Data Exchange System (VDES) using advanced FPGA techniques. The ideal candidate will have over 5 years of experience in FPGA development and knowledge of signal processing.

This role emphasizes collaboration and requires expertise in communications, FPGA toolchains, and SDR platforms. A Bachelor's degree in Telecommunications or Electrical Engineering is essential.

Qualificações

• 5+ years of professional FPGA development required.
• Experience developing on SDR platforms.
• Knowledge of digital communications, including synchronization and equalization.

Responsabilidades

• Design and implement the full VDES Physical Layer in FPGA logic.
• Analyse and implement technical requirements for global maritime compliance.
• Develop and optimize high-performance DSP blocks.
• Utilize SDR ecosystems for data flow management.
• Build comprehensive simulation environments and HIL test suites.
• Define efficient interfaces for processed data.

Conhecimentos

FPGA development (Verilog)

SDR platforms

Digital communications knowledge

Xilinx Vivado

Intel Quartus

MATLAB/Simulink

Problem-solving

Collaborative skills

Formação académica

Bachelor’s degree in Telecommunications Engineering

Bachelor’s degree in Electrical/Electronics Engineering

Master’s degree

Ferramentas

Xilinx Vivado

Intel Quartus

MATLAB

Simulink

Descrição da oferta de emprego

Role Overview

We are seeking a Senior FPGA Engineer with 5+ years of experience to work on the development of a VHF Data Exchange System (VDES) maritime radio using high-end Software Defined Radio (SDR) platforms. You will be the primary architect of the digital signal processing chain, responsible for interpreting international maritime standards and implementing them directly into FPGA. The goal is to deliver a production‑ready VDES stack that maximizes the capabilities of professional‑grade SDR hardware.

Key Responsibilities

• VDES PHY Layer Implementation: Design and implement the full VDES Physical Layer in FPGA logic, including modulation schemes (Pi/4 QPSK, 8PSK, 16QAM) and Forward Error Correction.
• Standards Interpretation: Analyse and implement technical requirements to ensure the radio meets global maritime compliance.
• Advanced DSP Design: Develop and optimize high-performance DSP blocks.
• SDR Framework Integration: Utilize SDR ecosystems to manage data flow between the FPGA fabric and host processing environments.
• System Verification: Build comprehensive simulation environments and hardware‑in‑the‑loop (HIL) test suites to validate radio performance.
• Software/Hardware Interface: Define and implement efficient interfaces to pass processed data to higher‑level network layers.

Qualification

Minimum Education

• Bachelor’s degree in:
  • Telecommunications Engineering
  • Electrical/Electronics Engineering
• Master’s degree is a plus.

Required Skills

• Experience: 5+ years of professional FPGA development (Verilog).
• SDR knowledge: Experience developing on SDR platforms.
• Communication Theory: Knowledge of digital communications, including synchronization, equalization, and spectral mask management.
• FPGA Toolchains: Xilinx Vivado (Zynq/UltraScale+) or Intel Quartus (Cyclone/Arria), including IP Integrator and HLS (High‑Level Synthesis).
• Modeling & Simulation: MATLAB/Simulink for algorithmic modeling and bit‑true verification against RTL.
• Standard‑Driven: A methodical approach to reading and implementing dense technical specifications.
• Problem Solver: Ability to debug complex timing and signal integrity issues within the SDR fabric.
• Collaborative: Experience working alongside software and hardware engineers to optimize the boundary between FPGA logic, hardware and C++/Python application code.