Senior RTL Engineer - SoC & Digital Design

Capgemini Engineering; Województwo mazowieckie; Hybride; PLN 180 000 - 320 000; Plein temps

Avantages offerts par ce poste

Medical care (Medicover)

Private life insurance

Sports card

Résumé du poste

Capgemini Engineering is seeking a Digital Design expert to lead the development of next-generation SoCs and digital IPs. You will drive functional specifications, design microarchitectures, and ensure RTL correctness across cross-functional teams in a cutting-edge semiconductor environment.

The role requires 7+ years in digital design, strong Verilog/VHDL skills, and familiarity with SystemVerilog and industry tools.

Qualifications

• 7+ years of hands-on experience in digital design.
• Proficiency in Verilog and/or VHDL; SystemVerilog is a plus.
• Experience with RTL design, uArch development, and functional specs.
• Familiarity with linting tools, CDC methodologies, and debugging flows.
• Experience with synthesis tools and SoC design is a strong plus.

Responsabilités

• Lead Functional Specification Development for advanced digital systems.
• Design and implement Microarchitecture (uArch) for high-performance blocks.
• Perform RTL Debugging, ensuring design correctness and efficiency.
• Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks.
• Collaborate with verification, physical design, and architecture teams.
• Contribute to Front-End Synthesis and optimization (bonus).
• Experience on SoC-level integration and design (nice to have).
• Apply Power Optimization Techniques for energy-efficient designs (nice to have).

Connaissances

Digital design experience

Verilog

VHDL

SystemVerilog

RTL design

uArch development

Linting tools

CDC methodologies

Debugging flows

SoC design

Formation

Bachelor's degree in EE/ECE/CE/CS

MS or PhD highly desired

Outils

Cadence Genus

Synopsys Design Compiler (DC)

Fusion Compiler

Description du poste

Capgemini Engineering is seeking a Digital Design expert to lead the development of next-generation SoCs and digital IPs. You will drive functional specifications, design microarchitectures, and ensure RTL correctness across cross-functional teams in a cutting-edge semiconductor environment.

The role requires 7+ years in digital design, strong Verilog/VHDL skills, and familiarity with SystemVerilog and industry tools.