Senior RTL Designer for SoC & Digital IP - Hybrid

Capgemini Engineering; Województwo opolskie; Hybrid; PLN 180.000 - 280.000; Vollzeit

Benefits dieser Stelle

Medicover medical care

Private life insurance

Sports card

Capgemini Helpline for wellbeing

Hybrid working model

Zusammenfassung

Capgemini Engineering is seeking a seasoned Digital Design expert to take on complex SoC projects. You will drive functional specs, design microarchitectures, and lead RTL debugging across cross‑functional teams. The role rewards deep RTL expertise and strong collaboration within a global engineering ecosystem.

Hunt for high-performance digital blocks, apply lint/CDC checks, and contribute to front-end synthesis. A/B testing of power optimizations and SoC integration are welcome additions.

Qualifikationen

• 7+ years of hands-on experience in digital design.
• Strong knowledge of Verilog and/or VHDL.
• Familiarity with SystemVerilog a plus.
• Experience with RTL design and uArch development.
• Proven debugging, linting, and CDC methodologies.
• Synthesis and SoC design familiarity a strong plus.

Aufgaben

• Lead Functional Specification Development for advanced digital systems.
• Design and implement Microarchitecture (uArch) for high-performance blocks.
• Perform RTL Debugging, ensuring design correctness and efficiency.
• Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks.
• Collaborate with verification, physical design, and architecture teams.
• Bonus: Front-End Synthesis and optimization.
• Nice to have: SoC-level integration experience.
• Nice to have: Power optimization techniques.

Kenntnisse

Verilog/VHDL

SystemVerilog

RTL design

uArch development

Debugging & linting

Collaboration

Communication

Ausbildung

Bachelor's in EE/EC/CE/CS

MS or PhD desirable

Tools

Cadence Genus

Synopsys DC

Fusion Compiler

Jobbeschreibung

Capgemini Engineering is seeking a seasoned Digital Design expert to take on complex SoC projects. You will drive functional specs, design microarchitectures, and lead RTL debugging across cross‑functional teams. The role rewards deep RTL expertise and strong collaboration within a global engineering ecosystem.

Hunt for high-performance digital blocks, apply lint/CDC checks, and contribute to front-end synthesis. A/B testing of power optimizations and SoC integration are welcome additions.