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Capgemini Engineering is seeking a Senior Digital Design expert to lead RTL uArch for advanced SoC blocks in the semiconductor space. You will design microarchitectures and guide verification and front-end teams across a hybrid work model.
Requires 7+ years in digital design, strong Verilog/VHDL, SystemVerilog a plus, and familiarity with Cadence Genus, Synopsys DC or Fusion Compiler. MS/PhD preferred; excellent collaboration skills.
Capgemini Engineering is seeking a Senior Digital Design expert to lead RTL uArch for advanced SoC blocks in the semiconductor space. You will design microarchitectures and guide verification and front-end teams across a hybrid work model.
Requires 7+ years in digital design, strong Verilog/VHDL, SystemVerilog a plus, and familiarity with Cadence Genus, Synopsys DC or Fusion Compiler. MS/PhD preferred; excellent collaboration skills.