Senior RTL & SoC Design Engineer (Hybrid)

Capgemini Engineering

Województwo pomorskie

Hybrid

PLN 180.000 - 240.000

Vollzeit

Vor 7 Tagen
Sei unter den ersten Bewerbenden

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Benefits dieser Stelle

Medicover medical care
Private life insurance
Sports card
Capgemini Helpline with wellbeing
Access to NEXT platform training

Zusammenfassung

Capgemini Engineering is seeking a Senior Digital Design expert to lead RTL uArch for advanced SoC blocks in the semiconductor space. You will design microarchitectures and guide verification and front-end teams across a hybrid work model.

Requires 7+ years in digital design, strong Verilog/VHDL, SystemVerilog a plus, and familiarity with Cadence Genus, Synopsys DC or Fusion Compiler. MS/PhD preferred; excellent collaboration skills.

Qualifikationen

  • 7+ years of hands-on experience in digital design.
  • Bachelor's degree in EE, ECE, CE, CS, or related field.

Aufgaben

  • Lead Functional Specification Development for advanced digital systems.
  • Design and implement Microarchitecture (uArch) for high-performance blocks.
  • Perform RTL Debugging, ensuring design correctness and efficiency.
  • Run and analyze Lint Checks and CDC (Clock Domain Crossing) Checks.
  • Collaborate with verification, physical design, and architecture teams.
  • Bonus: Front-End Synthesis and optimization.
  • Nice to have: SoC-level integration and design.
  • Nice to have: Power optimization techniques for energy-efficient designs.

Kenntnisse

Digital design
Verilog
VHDL
SystemVerilog
RTL debugging
uArch development
Collaboration

Ausbildung

Bachelor's degree in EE/CE/CS
MS or PhD highly desired

Tools

Cadence Genus
Synopsys Design Compiler (DC)
Fusion Compiler

Jobbeschreibung

Capgemini Engineering is seeking a Senior Digital Design expert to lead RTL uArch for advanced SoC blocks in the semiconductor space. You will design microarchitectures and guide verification and front-end teams across a hybrid work model.

Requires 7+ years in digital design, strong Verilog/VHDL, SystemVerilog a plus, and familiarity with Cadence Genus, Synopsys DC or Fusion Compiler. MS/PhD preferred; excellent collaboration skills.

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