DFT Engineer

Delos Data Inc; Poland; On-site; PLN 594,574 - 817,539; Full time

Benefits offered by this job

Meaningful equity

Benefits

401(k) plan

Job summary

A stealth-mode technology startup in Poland is seeking a DFT Verification Engineer to ensure the quality of ASIC DFT logic. You'll develop verification environments, execute plans, and collaborate with engineering teams. Ideal candidates have 5+ years of experience in digital design verification and deep knowledge of UVM and SystemVerilog. The target salary ranges from $160,000 to $220,000 per year, with equity and benefits included.

Qualifications

• 5+ years of experience in digital design verification, with at least 2 in DFT verification specifically.
• Strong hands-on experience with UVM-based or similar verification methodologies.
• Clear written and verbal communication skills for cross-functional collaboration.

Responsibilities

• Develop and maintain RTL verification environments using UVM.
• Create and execute coverage-driven verification plans aligned with design specifications.
• Analyze simulation results, debug complex verification issues.

Skills

UVM-based verification methodologies

SystemVerilog

Scripting (Python)

Problem-solving skills

Cross-functional collaboration

Education

Bachelor's or Master’s degree in Electrical Engineering or related field

Tools

Synopsys VCS

Mentor Questa

Cadence Xcelium

Synopsys TestMax

Siemens Tessent

Job description

DFT Verification Engineer

Who we are:

We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

What we need:

An experienced DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role focuses on building robust verification environments, executing coverage-driven verification plans, and working closely with DFT design engineers and manufacturing engineers to deliver reliable, high-quality silicon. The ideal candidate has deep hands‑on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows, and is comfortable driving verification efforts from planning through closure. The ideal candidate is also knowledgeable about DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes. Should have experience with gate-level simulation and tester pattern formats such as STIL.

Key Responsibilities:

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
• Create and execute coverage-driven verification plans aligned with design specifications
• Use EDA DFT tools (e.g., TestMax, Tessent) to create and run recommended pre-silicon test cases for MBIST and scan fabric inserted by those tools
• Develop directed test cases for other (non-vendor-supplied) DFT logic to validate functionality and identify corner cases
• Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences
• Analyze simulation results, debug complex verification and design issues, and perform root‑cause analysis in collaboration with DFT design engineers
• Implement and track functional and code coverage, driving verification to closure
• Develop reusable verification components and write SystemVerilog Assertions (SVA)
• Participate in design and verification reviews, providing input on design testability, correctness, and optimization
• Automate regression testing and enhance verification infrastructure using Python and scripting
• Contribute to continuous improvement of verification processes, tools, and methodologies
• Along with the DFT designers, help support post-silicon test bring‑up debug

Required Skills and Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of experience in digital design verification, with at least 2 in DFT verification specifically
• Strong hands‑on experience with UVM‑based or similar verification methodologies
• Proficiency in SystemVerilog
• Experience in scripting (preferably Python) and automation
• Experience with industry‑standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
• Experience with industry‑standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent)
• Solid understanding of digital design fundamentals
• Experience with verification of test sequences for high‑speed PHY logic including PCIe and Ethernet (10G/40G/100G)
• Strong analytical and problem‑solving skills
• Clear written and verbal communication skills for cross‑functional collaboration
• High attention to detail and ability to deliver reliable, high‑quality verification outcomes
• Ability to work independently and manage tasks to completion

Desired Skills:

• Experience with change control systems, especially git
• Experience verifying SoC‑level designs

Compensation:

Target base salary for this role is $160,000 – $220,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location.

Agency Note:

We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired.

We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics.