DFT Lead - SOC Test & Debug Leader

Capgemini Engineering; Wrocław; Hybrid; PLN 180,000 - 280,000; Full time

Benefits offered by this job

Well-being benefits

Extensive training tracks

Performance management tools

Job summary

Capgemini Engineering in Poland seeks an experienced DFT Lead to drive DFT and test-flow activities for advanced SOCs. You will implement DFT, supervise ATPG/MBIST, and collaborate with physical design to meet timing and performance targets.

You will guide a multi-site team, debug timing issues, and optimize test coverage while working in a hybrid office/remote model and leveraging a broad toolset across industry-standard EDA platforms.

Qualifications

• 6+ years of hands-on experience with DFT and test flows for large and complex SOCs.
• Strong knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST.
• Experience with leading EDA tools such as Synopsys DFT Compiler, Tetramax, VCS, Tessent and Modus/Encounter.

Responsibilities

• DFT implementation inline with existing test methodology for advanced process nodes.
• Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST.
• Closely work with physical design team to resolve timing constraints/issues.
• Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues.
• Debug and improve important DFT KPIs: test coverage/pattern efficiency.
• Hierarchical retargeting.
• Silicon bring-up, diagnosis and support for physical failure analysis.
• Opportunity to lead a multilocational team of DFT engineers.

Skills

DFT

JTAG

ATPG

MBIST/LBIST

RTL simulation

Perl scripting

Python scripting

IEEE 1500

Tools

Synopsys DFT Compiler

Tetramax

VCS

Tessent

Modus/Encounter

Job description

Capgemini Engineering in Poland seeks an experienced DFT Lead to drive DFT and test-flow activities for advanced SOCs. You will implement DFT, supervise ATPG/MBIST, and collaborate with physical design to meet timing and performance targets.

You will guide a multi-site team, debug timing issues, and optimize test coverage while working in a hybrid office/remote model and leveraging a broad toolset across industry-standard EDA platforms.