DFT Lead Multilocational SOC Engineering Lead

Capgemini Engineering

Kraków

Hybrid

PLN 180,000 - 240,000

Full time

14 days+

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Benefits offered by this job

Hybrid working model
Training & development opportunities
Well-being program

Job summary

Capgemini Engineering seeks a DFT Lead to join our engineering team and drive design-for-test flows for complex SOCs. You will collaborate across multiple VLSI domains including design, verification, timing, and reliability to implement robust DFT solutions.

You’ll lead a multi-location team, optimize test coverage, and work with industry-standard EDA tools to ensure high-quality silicon bring-up and failure analysis support. Hybrid work model offered.

Qualifications

  • 6+ years of hands-on experience with DFT and test flows for large and complex SOCs.
  • Strong knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST.

Responsibilities

  • DFT implementation in line with existing test methodology for advanced process nodes.
  • Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST.
  • Collaborate with physical design to resolve timing constraints/issues.
  • Verify DFT circuitry and interface with other components/IPs; debug timing issues.
  • Improve DFT KPIs: test coverage and pattern efficiency.
  • Lead a multilocational team of DFT engineers.

Skills

DFT techniques
RTL simulation
Analytical skills
Problem solving
JTAG/ATPG knowledge
Perl scripting
Python scripting

Tools

Synopsys DFT Compiler
Tetramax
VCS
Tessent
Encounter/Modus

Job description

Capgemini Engineering seeks a DFT Lead to join our engineering team and drive design-for-test flows for complex SOCs. You will collaborate across multiple VLSI domains including design, verification, timing, and reliability to implement robust DFT solutions.

You’ll lead a multi-location team, optimize test coverage, and work with industry-standard EDA tools to ensure high-quality silicon bring-up and failure analysis support. Hybrid work model offered.

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