FPGA Developer - Poland

GTS; Warszawa; On-site; PLN 253,807 - 359,560; Full time

Job summary

GTS is seeking a senior hardware engineer in Warsaw, Poland, to join our growing FPGA team. You will work on cutting-edge FPGA technology, contributing to full-stack systems from architecture and implementation to performance optimization.

The ideal candidate has over 5 years of experience in FPGA or ASIC design, expertise in Verilog, SystemVerilog, or VHDL, and familiarity with modern FPGA architectures. Join us to make impactful contributions in a highly collaborative environment.

Qualifications

• 5+ years of commercial FPGA or ASIC experience as a hardware design engineer.
• Strong logic design expertise using Verilog, SystemVerilog, VHDL, or SystemC.
• Familiarity with modern FPGA architectures such as Xilinx UltraScale+ or Intel Stratix 10.

Responsibilities

• Work on full-stack FPGA systems in a collaborative environment.
• Contribute to architecture, implementation, and verification of systems.
• Optimize performance and improve tooling/CI processes.

Skills

FPGA or ASIC experience

Logic design using Verilog, SystemVerilog, VHDL, or SystemC

Understanding of modern FPGA architectures

Experience with EDA tools

Verification methodologies

Static timing analysis

Linux driver or kernel development

C/C++/Python programming

HLS experience

SpinalHDL/Chisel experience

Job description

Overview

We are looking to hire a senior hardware engineer to join a small and growing FPGA team developing key components of a high-performance FPGA platform. This role offers broad technical scope and exposure across multiple layers of computing technology, from RTL and verification to high-speed interfaces and system integration.

Responsibilities

Successful candidates will work on full-stack FPGA systems in a highly collaborative environment, contributing to architecture, implementation, verification, performance optimization, and tooling/CI improvements.

Qualifications

• 5+ years of commercial FPGA or ASIC experience as a hardware design engineer
• Strong logic design expertise using Verilog, SystemVerilog, VHDL, or SystemC
• Familiarity with modern FPGA architectures such as Xilinx UltraScale+ or Intel Stratix 10
• Experience with one or more of:
  • 10/25/100GbE Ethernet
  • PCIe and DMA
  • NVMe
  • DDR / QDR / HBM memory systems
• Experience with EDA tools from vendors such as Xilinx/AMD, Synopsys, Cadence, or Siemens EDA/Mentor Graphics
• Experience with verification methodologies and frameworks such as Cocotb, UVM, or SystemVerilog Assertions is a plus
• Static timing analysis experience is a plus
• Linux driver or kernel development experience is a plus
• C/C++/Python experience is a plus
• HLS experience is a plus
• SpinalHDL/Chisel experience is a plus

Note: The use of AI tools during interviews is strictly prohibited, unless explicitly agreed upon.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, age, national origin, or protected veteran status, and will not be discriminated against on the basis of disability.