VLSI Verification Engineer

Jobtailor; Województwo pomorskie; On-site; PLN 120,000 - 170,000; Full time

Job summary

Jobtailor seeks an experienced ASIC/SoC verification engineer to design and implement robust UVM-based verification environments. You will work on architecture-aligned verification plans, leveraging constrained-random techniques to improve coverage.

You will collaborate with RTL designers and validation teams to validate high‑speed interfaces and memory subsystems, debugging HW/SW interactions with industry tools. Prior experience with AXI/PCIe is preferred.

Qualifications

• Minimum 5 years of hands-on ASIC/SoC verification.
• Strong proficiency in SystemVerilog, UVM, and constrained-random verification.
• Solid understanding of digital design principles and RTL coding (Verilog/VHDL).
• Experience with EDA simulation and debug tools from major vendors.
• Proven ability to debug complex digital logic and HW/SW interactions.
• Familiarity with protocols such as AXI, PCIe, DDR, or CXL (preferred).
• Experience building UVM environments from scratch (preferred).

Responsibilities

• Develop and execute verification plans based on architecture and RTL specifications.
• Build, extend, and maintain UVM-based verification environments, including agents, drivers, sequencers, monitors, scoreboards, and checkers.
• Implement constrained-random and coverage-driven verification methodologies.
• Debug complex hardware and hardware/software interactions using industry-standard tools.
• Collaborate with RTL designers, architects, and validation teams to identify issues and drive them to closure.
• Analyze functional coverage, identify gaps, and ensure verification completeness.
• Participate in subsystem and SoC-level integration and verification activities.

Skills

SystemVerilog

UVM

Constrained-Random

RTL Coding

Verilog

VHDL

Debugging

Digital Design

AXI

PCIe

DDR

CXL

Education

B.Sc. or M.Sc. in Electrical or Computer Engineering

Tools

Synopsys Tools

Cadence Tools

Mentor/Siemens Tools

Job description

• Develop and execute verification plans based on architecture and RTL specifications.
• Build, extend, and maintain UVM-based verification environments, including agents, drivers, sequencers, monitors, scoreboards, and checkers.
• Implement constrained-random and coverage-driven verification methodologies.
• Debug complex hardware and hardware/software interactions using industry-standard tools.
• Collaborate with RTL designers, architects, and validation teams to identify issues and drive them to closure.
• Analyze functional coverage, identify gaps, and ensure verification completeness.
• Participate in subsystem and SoC-level integration and verification activities.

Requirements

• B.Sc . or M.Sc . in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 5 years of hands‑on experience in ASIC/SoC verification.
• Strong proficiency in SystemVerilog , UVM , and constrained‑random verification.
• Solid understanding of digital design principles and RTL coding (Verilog/VHDL).
• Experience with EDA simulation and debug tools from Synopsys, Cadence, or Siemens/Mentor.
• Proven ability to debug complex digital logic and HW/SW interactions.
• Strong analytical mindset, communication skills, and ability to work in multidisciplinary teams.
• Experience with high‑speed interfaces, memory subsystems, or AI/ML accelerators (preferred).
• Familiarity with protocols such as AXI, PCIe, DDR, or CXL (preferred).
• Experience building UVM environments from scratch (preferred).

Core Competencies

Demonstrates expertise in ASIC/SoC verification, including the development of UVM-based verification environments and the implementation of constrained-random verification methodologies. Proficient in debugging complex hardware and software interactions while collaborating effectively with multidisciplinary teams.

Highest-signal resume keywords

• ASIC/SoC Verification
• SystemVerilog
• UVM
• Constrained-Random Verification
• EDA Simulation Tools

ATS Optimization Keywords

Hard Skills

• Digital Design Principles
• RTL Coding
• Verilog
• VHDL
• Debugging Complex Digital Logic
• Functional Coverage Analysis
• High-Speed Interfaces
• Memory Subsystems
• AI/ML Accelerators
• Building UVM Environments

Soft Skills

• Analytical Mindset
• Communication Skills
• Collaboration

Industry Keywords

• Verification Plans
• RTL Specifications
• Subsystem Integration
• SoC-Level Verification
• Protocols
• AXI
• PCIe
• DDR
• CXL

Tools & Technologies

• Synopsys Tools
• Cadence Tools
• Siemens/Mentor Tools