A stealth-mode technology startup in Poland is seeking a DFT Verification Engineer to ensure the quality of ASIC DFT logic. You'll develop verification environments, execute plans, and collaborate with engineering teams. Ideal candidates have 5+ years of experience in digital design verification and deep knowledge of UVM and SystemVerilog. The target salary ranges from $160,000 to $220,000 per year, with equity and benefits included.
Qualifications
5+ years of experience in digital design verification, with at least 2 in DFT verification specifically.
Strong hands-on experience with UVM-based or similar verification methodologies.
Clear written and verbal communication skills for cross-functional collaboration.
Responsibilities
Develop and maintain RTL verification environments using UVM.
Create and execute coverage-driven verification plans aligned with design specifications.
Bachelor's or Master’s degree in Electrical Engineering or related field
Tools
Synopsys VCS
Mentor Questa
Cadence Xcelium
Synopsys TestMax
Siemens Tessent
Job description
A stealth-mode technology startup in Poland is seeking a DFT Verification Engineer to ensure the quality of ASIC DFT logic. You'll develop verification environments, execute plans, and collaborate with engineering teams. Ideal candidates have 5+ years of experience in digital design verification and deep knowledge of UVM and SystemVerilog. The target salary ranges from $160,000 to $220,000 per year, with equity and benefits included.