Senior ASIC RTL Architect — Subsystems & Tapeouts

Synopsys, Inc.; Hinoba-an; On-site; PHP 900,000 - 1,500,000; Full time

Job summary

Synopsys, Inc. in the Philippines seeks an experienced RTL design engineer to own complex subsystem design from spec to release.

You will craft architecture, write production-quality RTL, and collaborate with verification, synthesis, STA, and DFT teams to ensure timing closure and robust design blocks. Lead integration of PCIe, DDR, UFS, USB, and AMBA interconnects while applying low power techniques across multiple voltage domains.

Qualifications

• Bachelor's or master's in electronics, electrical, or computer engineering or equivalent.
• 8+ years of hands-on RTL design with multiple tape-outs in complex IP/subsystems/SoC blocks.
• Proficiency with Verilog or SystemVerilog and synthesizable, timing-clean RTL.

Responsibilities

• Own full lifecycle of complex subsystem design from requirements to release.
• Craft architecture and write production-quality RTL using best practices.
• Drive RTL quality checks including lint, CDC, RDC, and verification collaboration.
• Integrate standard protocols like PCIe, DDR, UFS, USB, and AMBA interconnects.
• Implement low power techniques across clock gating, power gating, and multi-voltage domains.
• Collaborate with logic synthesis, STA, and physical design to ensure timing closure.
• Work with DFT teams to architect scan, MBIST, and testability features.

Skills

RTL design

Verilog/SystemVerilog

Low power design

DFT concepts

Cross-functional collaboration

Timing closure

Education

Bachelor's or Master's in Electronics/Electrical/Computer Engineering

Tools

Synthesis tools

Job description

Synopsys, Inc. in the Philippines seeks an experienced RTL design engineer to own complex subsystem design from spec to release.

You will craft architecture, write production-quality RTL, and collaborate with verification, synthesis, STA, and DFT teams to ensure timing closure and robust design blocks. Lead integration of PCIe, DDR, UFS, USB, and AMBA interconnects while applying low power techniques across multiple voltage domains.