Senior CAD & Methodology Architect — RTL to GDSII

Renesas Electronics Corporation; Hinoba-an; On-site; PHP 2,000,000 - 3,200,000; Full time

Job summary

Renesas Electronics Corporation seeks a proactive CAD & Methodology Engineer to develop and support scalable design automation for Backend Physical Design teams. You will enable efficient RTL-to-GDSII implementation, maintain robust reference flows, and drive standardization across projects.

The role collaborates with Physical Design, Timing, Signoff, EDA vendors, IT, and Foundry partners to ensure smooth tool deployment, optimized methodologies, and timely tapeouts.

Qualifications

• Bachelor's or Master's degree in Electronics or Electrical Engineering.
• 10+ years in Physical Design CAD, Design Methodology, or Backend Design Automation.
• Strong RTL-to-GDSII implementation and signoff knowledge.
• Hands-on with industry-standard EDA tools (Synopsys, Cadence, Siemens).
• Proficiency in Tcl, Python, Shell, or Perl scripting.
• Experience developing CAD automation for backend design teams.

Responsibilities

• Develop, maintain, and release reference flows for Synthesis, STA, Place & Route, and Signoff.
• Build automation to improve productivity, including setup generation, QoR checks, report parsing, ECO automation, and deliverable packaging.
• Define and enforce methodology standards, flow validation, and QoR compliance checks.
• Qualify and deploy EDA tools, PDKs, libraries, and signoff runsets across compute environments.
• Provide technical support and root‑cause analysis for flow, tool, and infrastructure issues through tapeout.
• Collaborate with Physical Design teams, IT, EDA vendors, and Foundry partners to drive flow improvements and issue resolution.

Skills

PD CAD

Design Methodology

Backend Automation

EDA Tools

Python/Tcl scripting

EE Degree

Education

EE Degree

Tools

Synopsys

Cadence

Siemens

Job description

Renesas Electronics Corporation seeks a proactive CAD & Methodology Engineer to develop and support scalable design automation for Backend Physical Design teams. You will enable efficient RTL-to-GDSII implementation, maintain robust reference flows, and drive standardization across projects.

The role collaborates with Physical Design, Timing, Signoff, EDA vendors, IT, and Foundry partners to ensure smooth tool deployment, optimized methodologies, and timely tapeouts.