Senior IP Modeling Engineer — Verilog & SystemC

Lattice Semiconductor (PH) Corporation; Manila; On-site; PHP 900,000 - 1,300,000; Full time

Job summary

Lattice Semiconductor is seeking a Senior Design Engineer – Modeling to develop, validate, and deliver IP behavioral models and hardware collateral for internal engineering teams and customers. You will translate IP specs into accurate models and drive validation, automation, and methodology improvements across multiple projects.

The role requires collaboration with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to ensure model quality, scalability,

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• Senior-level experience in digital, custom, analog, FPGA, ASIC, or IP modeling and verification.
• Strong understanding of digital design fundamentals, RTL concepts, and simulation.
• Proficiency in Verilog and/or SystemVerilog for modeling and simulation.

Responsibilities

• Develop and maintain IP models using Verilog, SystemVerilog, and SystemC/C++ where applicable.
• Translate IP specifications into model requirements, implementation plans, and verification objectives.
• Perform functional testing, lint and CDC checks, regression testing, and comparisons against hardware references and specs.
• Lead generation, audit, validation, and release of timing, power, and metadata deliverables for hardware/software integration.
• Investigate and resolve model-related and HW/SW integration issues across the IP development lifecycle.
• Develop scripts and reusable workflows to improve model generation, validation, audit, release, traceability, and reporting.
• Collaborate with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams.
• Lead technical reviews, mentor engineers, and promote consistent modeling and verification practices.
• Identify quality or process gaps and drive improvements to reduce manual effort and accelerate turnaround time.

Skills

Verilog

SystemVerilog

Python

Perl

TCL

Shell

Digital design fundamentals

RTL concepts

Simulation

Modeling

Collaboration

Education

Bachelor or Master in EE

Tools

SPICE-type simulation

XML

SystemC

C++

Job description

Lattice Semiconductor is seeking a Senior Design Engineer – Modeling to develop, validate, and deliver IP behavioral models and hardware collateral for internal engineering teams and customers. You will translate IP specs into accurate models and drive validation, automation, and methodology improvements across multiple projects.

The role requires collaboration with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to ensure model quality, scalability,