Senior IP Modeling Engineer

Lattice Semiconductor (PH) Corporation; Manila; On-site; PHP 900,000 - 1,500,000; Full time

Job summary

Lattice Semiconductor (PH) Corporation seeks a Senior Design Engineer – Modeling to develop, validate, and deliver IP behavioral models and hardware collateral. You’ll translate IP specs into accurate models and drive validation, automation, and methodology improvements across multiple projects.

You will collaborate closely with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to align requirements, ownership, and delivery schedules while mentoring

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Senior-level experience in digital, custom, analog, FPGA, ASIC, or IP modeling and verification environments.
• Strong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow.
• Proficiency in Verilog and/or SystemVerilog for functional or behavioral modeling and simulation.
• Working knowledge of semiconductor and IC principles including device behavior, layout, timing, power, and signal integrity.
• Experience with digital simulation tools and familiarity with SPICE-type simulation, device models, or transistor-level design concepts.
• Experience with scripting or programming languages such as Python, Perl, TCL, or Shell for automation.
• Ability to develop verification plans, define measurable completion criteria, analyze results, and drive issues to closure.
• Strong collaboration and teamwork skills across multi-site and cross-functional teams.
• Good written and verbal communication skills.

Responsibilities

• Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.
• Translate IP specs, schematics, RTL, and design intent into model requirements and verification objectives.
• Perform functional testing, audits, lint and CDC checks, regression testing, and consistency checks against hardware references.
• Lead or support generation, audit, validation, and release of timing, power, and metadata deliverables for hardware/software integration.
• Investigate and resolve model behavior and hardware-software integration issues across the IP development lifecycle.
• Develop scripts and workflows to improve model generation, validation, audit, release, and traceability.
• Collaborate with IP Design/Verification/Integration/Software/Architecture/Applications teams to align requirements and delivery schedules.
• Lead technical reviews, mentor engineers, and promote consistent modeling and verification practices.
• Identify quality or process gaps and drive improvements to reduce manual effort and shorten turnaround time.

Skills

Verilog/SystemVerilog

IP modeling

Python scripting

Digital/analog design fundamentals

RTL concepts

Collaboration across teams

Communication skills

Debugging/validation

Education

Bachelor’s or Master’s in Electrical/Electronic/Computer Engineering

Tools

SystemC

C++

SPICE-type simulation

Job description

Lattice Semiconductor (PH) Corporation seeks a Senior Design Engineer – Modeling to develop, validate, and deliver IP behavioral models and hardware collateral. You’ll translate IP specs into accurate models and drive validation, automation, and methodology improvements across multiple projects.

You will collaborate closely with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to align requirements, ownership, and delivery schedules while mentoring