Design Eng - Modeling

Lattice Semiconductor (PH) Corporation; Manila; On-site; PHP 900,000 - 1,500,000; Full time

Job summary

Lattice Semiconductor (PH) Corporation seeks a Senior Design Engineer – Modeling to develop, validate, and deliver IP behavioral models and hardware collateral. You’ll translate IP specs into accurate models and drive validation, automation, and methodology improvements across multiple projects.

You will collaborate closely with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to align requirements, ownership, and delivery schedules while mentoring

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Senior-level experience in digital, custom, analog, FPGA, ASIC, or IP modeling and verification environments.
• Strong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow.
• Proficiency in Verilog and/or SystemVerilog for functional or behavioral modeling and simulation.
• Working knowledge of semiconductor and IC principles including device behavior, layout, timing, power, and signal integrity.
• Experience with digital simulation tools and familiarity with SPICE-type simulation, device models, or transistor-level design concepts.
• Experience with scripting or programming languages such as Python, Perl, TCL, or Shell for automation.
• Ability to develop verification plans, define measurable completion criteria, analyze results, and drive issues to closure.
• Strong collaboration and teamwork skills across multi-site and cross-functional teams.
• Good written and verbal communication skills.

Responsibilities

• Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.
• Translate IP specs, schematics, RTL, and design intent into model requirements and verification objectives.
• Perform functional testing, audits, lint and CDC checks, regression testing, and consistency checks against hardware references.
• Lead or support generation, audit, validation, and release of timing, power, and metadata deliverables for hardware/software integration.
• Investigate and resolve model behavior and hardware-software integration issues across the IP development lifecycle.
• Develop scripts and workflows to improve model generation, validation, audit, release, and traceability.
• Collaborate with IP Design/Verification/Integration/Software/Architecture/Applications teams to align requirements and delivery schedules.
• Lead technical reviews, mentor engineers, and promote consistent modeling and verification practices.
• Identify quality or process gaps and drive improvements to reduce manual effort and shorten turnaround time.

Skills

Verilog/SystemVerilog

IP modeling

Python scripting

Digital/analog design fundamentals

RTL concepts

Collaboration across teams

Communication skills

Debugging/validation

Education

Bachelor’s or Master’s in Electrical/Electronic/Computer Engineering

Tools

SystemC

C++

SPICE-type simulation

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description

Summary

The Senior Design Engineer – Modeling position develops, validates, and delivers IP behavioral models and related hardware collateral used by internal engineering teams and software-facing customers. The role translates IP specifications and hardware design intent into accurate, efficient, and maintainable models, while ensuring consistency with custom, analog, or digital implementations.

The engineer also drives validation, automation, and methodology improvements that strengthen model quality, scalability, and delivery efficiency across multiple projects. The position requires close collaboration with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams.

Key Responsibilities

• Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.
• Translate IP specifications, schematics, RTL, and design intent into clear model requirements, implementation plans, and verification objectives.
• Perform functional testing, audits, lint and CDC checks, regression testing, and consistency or equivalency checks against approved hardware references and specifications.
• Lead or support the generation, audit, validation, and release of timing, power, signal‑integrity, configuration, and metadata deliverables used for hardware and software integration.
• Investigate and resolve model behavior, hardware-to-software integration, and customer‑facing issues across the IP development lifecycle.
• Develop scripts and reusable workflows that improve model generation, validation, audit, release, traceability, and reporting.
• Partner with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams to align requirements, ownership, quality expectations, and delivery schedules.
• Lead technical reviews, provide sound engineering direction, mentor less‑experienced engineers, and promote consistent modeling and verification practices.
• Identify quality or process gaps and drive practical improvements that reduce manual effort, improve scalability, and shorten turnaround time.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• Demonstrated senior-level experience in digital, custom, analog, FPGA, ASIC, or IP modeling and verification environments.
• Strong understanding of digital design fundamentals, RTL concepts, simulation, and the overall design and verification flow.
• Proficiency in Verilog and/or SystemVerilog for functional or behavioral modeling and simulation.
• Working knowledge of semiconductor and integrated‑circuit principles, including the effects of device behavior, layout, timing, power, and signal integrity on system behavior.
• Experience with digital simulation tools and familiarity with SPICE‑type simulation, device models, or transistor‑level design concepts.
• Experience with scripting or programming languages such as Python, Perl, TCL, or Shell for engineering automation.
• Ability to develop verification plans, define measurable completion criteria, analyze results, and drive technical issues to closure.
• Strong collaboration and teamwork skills, with openness to working across multi‑site and cross‑functional teams
• Good written and verbal communication skills, with the ability to ask clear questions, explain technical ideas, and learn from feedback

Preferred Qualifications

• Experience developing models that represent custom digital or analog IP behavior.
• Experience with timing, power, IBIS, signal‑integrity, configuration, XML, or other metadata‑based IP deliverables.
• Experience with model equivalency, regression automation, lint, CDC, or structured design‑quality audits.
• Familiarity with FPGA development platforms and integrated hardware‑software enablement flows.
• Experience improving engineering processes, creating reusable methods, or deploying automation across multiple projects.
• Experience mentoring engineers or providing technical leadership within a project team.

GenAI-Enabled Engineering Mindset

• Uses approved GenAI tools responsibly to support learning, code review, debugging, documentation, automation, and technical summarization.
• Proactively considers where GenAI can reduce repetitive work or improve quality, while independently verifying outputs and applying sound engineering judgment.
• Protects confidential and proprietary information and follows applicable company policies when using AI‑assisted tools.

#LI-DNP

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Philippines

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visitwww.latticesemi.com. You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates.