Senior IP Modeling Engineer

Lattice Semiconductor; Manila; On-site; PHP 1,500,000 - 2,300,000; Full time

Job summary

Lattice Semiconductor is seeking a Senior Design Engineer – Modeling to develop, validate, and deliver IP behavioral models and related hardware collateral. You will translate IP specifications into accurate models and drive validation and automation improvements, collaborating with multiple teams.

This role requires strong Verilog/SystemVerilog skills, scripting ability, and a track record in IP modeling; you will mentor engineers and help ensure high-quality designs across projects.

Qualifications

• Bachelor’s or Master’s degree in Electrical, Electronics, Computer Engineering, or related field.
• Senior-level experience in digital, custom, analog, FPGA/ASIC/IP modeling and verification.
• Strong understanding of digital design fundamentals, RTL, simulation and V&V flow.
• Proficiency in Verilog and/or SystemVerilog for modeling and simulation.
• Knowledge of device behavior, timing, power, and signal integrity effects on system behavior.
• Experience with scripting languages for automation (Python, Perl, TCL, Shell).
• Ability to develop verification plans and drive issues to closure.
• Excellent collaboration and communication across multi-site teams.

Responsibilities

• Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and SystemC/C++ where applicable.
• Translate IP specs and design intent into model requirements and verification objectives.
• Perform functional testing, lint, CDC checks, regression testing against hardware references.
• Lead generation, audit, validation, and release of timing, power, and metadata deliverables for integration.
• Investigate and resolve model, HW-SW integration, and customer-facing issues.
• Develop scripts and workflows to improve model generation, validation, and reporting.
• Collaborate with IP Design, Design Verification, Integration, Software, Architecture, and Applications teams.
• Lead technical reviews and mentor engineers to promote best practices.
• Identify gaps and drive improvements to reduce manual effort and shorten turnaround.

Skills

Verilog/SystemVerilog

Python scripting

RTL concepts

Digital design

Collaboration

Education

Bachelor’s or Master’s degree in Electrical/Electronics/Computer Engineering

Tools

SPICE-type simulation

XML/metadata IP deliverables

Job description

Lattice Semiconductor is seeking a Senior Design Engineer – Modeling to develop, validate, and deliver IP behavioral models and related hardware collateral. You will translate IP specifications into accurate models and drive validation and automation improvements, collaborating with multiple teams.

This role requires strong Verilog/SystemVerilog skills, scripting ability, and a track record in IP modeling; you will mentor engineers and help ensure high-quality designs across projects.