Senior Fullchip Integration Engineer

Lattice Semiconductor; Manila; On-site; PHP 600,000 - 1,200,000; Full time

Job summary

Lattice Semiconductor (PH) Corp. in Manila is seeking an Integration Design Engineer to join the Silicon Integration Team.

You will lead fullchip IP integration, coordinate with Architecture, SW, IP Design, and Physical Design teams, and ensure sign-off through comprehensive models and simulations. The role requires 5+ years in Custom and Digital Design with Verilog/SystemVerilog, FPGA/CPLD exposure, and strong synthesis, timing, DFT, and power analysis knowledge, plus familiarity with Cadence

Qualifications

• At least 5 years of proven in-depth experience in Custom and Digital Design Implementation.
• Expertise in Verilog and SystemVerilog is a must.
• Experience in FPGA/CPLD design and integration is a plus.
• Knowledge of standard design flows, DFT, timing, power, and verification.
• Experience with IP and fullchip integration and scripting is beneficial.

Responsibilities

• Design engineer will generally be responsible for the integration of different IPs to build the fullchip and deliver models, views and sign-off simulations.
• Collaborate with Architecture, SW, IP Design, and Physical Design Teams to generate fullchip floorplan and behavioral models, delivering synthesized netlists and schematics.
• Design and implement density-specific IPs and sectors, performing elaboration, synthesis, equivalence, DFT, timing closure, and power analysis.
• Work closely with other teams to debug and resolve issues.
• Conduct fullchip tapeout-gating audits including EMIR, NetERC, PDN extraction, SSO simulations, and ESD checks.

Skills

Verilog

SystemVerilog

FPGA/CPLD design

Digital design flow

RTL coding

Synthesis & timing

DFT flow

Power/performance analysis

Scripting (Perl/TCL/Shell)

Project leadership

Education

BS or MS in Electronics/Computer/Electrical Engineering

Tools

Cadence Virtuoso

Xcelium

Genus

Innovus

Tempus

Spice simulators

Job description

Lattice Semiconductor (PH) Corp. in Manila is seeking an Integration Design Engineer to join the Silicon Integration Team.

You will lead fullchip IP integration, coordinate with Architecture, SW, IP Design, and Physical Design teams, and ensure sign-off through comprehensive models and simulations. The role requires 5+ years in Custom and Digital Design with Verilog/SystemVerilog, FPGA/CPLD exposure, and strong synthesis, timing, DFT, and power analysis knowledge, plus familiarity with Cadence