Senior Full-Chip IP Integration Engineer

Lattice Semiconductor (PH) Corporation; Manila; On-site; PHP 1,200,000 - 2,400,000; Full time

Job summary

Lattice Semiconductor (PH) Corp. seeks an Integration Design Engineer to join the Silicon Integration Team. The engineer will integrate multiple IPs to form a fullchip using custom and digital flows, delivering models and collaterals for sign-off.

The role requires 5+ years in custom and digital design, with Verilog/SystemVerilog expertise and experience in FPGA/CPLD design. Collaboration across architecture, SW, IP, and physical design is essential.

Qualifications

• BS or MS in Electronics/Computer/Electrical Engineering required.
• Verilog/SystemVerilog expertise required for custom/digital design.

Responsibilities

• Integrate IPs to build fullchip and deliver models, views, and collaterals for sign-off.
• Coordinate with Architecture, SW, IP Design, and Physical Design teams for fullchip floorplan and netlist delivery.
• Design and implement density-specific IPs and sectors for fullchip integration, with timing and power checks.
• Collaborate with teams to debug issues and perform EMIR, PDN, and ESD checks.

Skills

EE Degree

Verilog / SystemVerilog

FPGA / CPLD

Cadence Virtuoso

RTL Coding & Verification

DFT / ATPG

Scripting Languages

Digital Design Flow

Project Leadership

Fullchip Integration

Timing / Power Analysis

Education

BS or MS in Electronics/Computer/Electrical Engineering

Tools

Cadence Virtuoso

Xcelium

Genus

Innovus

Tempus

Perl

TCL

Shell

Phyton

Job description

Lattice Semiconductor (PH) Corp. seeks an Integration Design Engineer to join the Silicon Integration Team. The engineer will integrate multiple IPs to form a fullchip using custom and digital flows, delivering models and collaterals for sign-off.

The role requires 5+ years in custom and digital design, with Verilog/SystemVerilog expertise and experience in FPGA/CPLD design. Collaboration across architecture, SW, IP, and physical design is essential.