Senior Full-Chip Integration Design Engineer

Lattice Philippines; Philippines; On-site; PHP 900,000 - 1,200,000; Full time

Job summary

Lattice Philippines is seeking an Integration Design Engineer to join the Silicon Integration Team. The role focuses on integrating multiple IP blocks to form a complete chip using both custom and digital design flows.

As part of the team, you will deliver fullchip netlists and schematics, work with Architecture, SW, IP, and Physical Design to ensure sign-off readiness, and perform rigorous verification and timing checks across the design flow.

Qualifications

• BS or MS in Electronics/Computer/Electrical Engineering.
• Expertise in Verilog and SystemVerilog; IP/Fullchip integration experience.
• Cadence Virtuoso and ASIC design-flow familiarity.

Responsibilities

• Integrate IPs to build fullchip.
• Deliver models, views, and checks for sign-off.
• Collaborate with Architecture, SW, IP Design, and Physical Design teams to generate fullchip floorplan.
• Create fullchip behavioral model by IP integration aligned to floorplan and SW/verification needs.
• Deliver fullchip netlist and schematics.
• Develop density-specific IPs (e.g., clock networks) for fullchip.
• Run flows: elaboration, synthesis, timing, DFT/ATPG, STA, power analysis.
• Debug with cross-functional teams.
• Conduct EM/IR drop, NetERC, PDN extraction, SSO, and ESD checks.

Skills

Verilog

SystemVerilog

FPGA/CPLD design

RTL coding

DFT/ATPG

Perl

TCL

Python

Cadence Virtuoso

IP/Fullchip integration

Education

Electronics Eng. degree

Tools

Xcelium

Genus

Innovus

Tempus

Job description

Lattice Philippines is seeking an Integration Design Engineer to join the Silicon Integration Team. The role focuses on integrating multiple IP blocks to form a complete chip using both custom and digital design flows.

As part of the team, you will deliver fullchip netlists and schematics, work with Architecture, SW, IP, and Physical Design to ensure sign-off readiness, and perform rigorous verification and timing checks across the design flow.