Senior IC Finishing Engineer - AI-Driven Flows, Flex Hours

Ampleon; Cabuyao; On-site; PHP 900,000 - 1,300,000; Full time

Job summary

Ampleon is seeking a Sr. Engineer, Chip Finishing to join the EST, Design Enablement team. You will work in the Philippines under the Principal Engineer, Design Enablement Team Lead, contributing to tile manipulation, DRC validation, and die‑bow checks.

You will coordinate with Design Engineers and Technology teams, ensure design quality for handoff to Mask Data Preparation, and help maintain process-flow documentation while supporting cross‑regional collaboration.

Qualifications

• Bachelor’s degree in electrical engineering or related field.
• 5 years of experience in semiconductor industry, preferably IC design.
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain root causes of violations in physical IC design.
• Familiarity with Linux and EDA tools (Synopsys, Cadence, Klayout).
• Scripting skills in Python, Bash or Tcl.
• Strong written and verbal English communication, problem solving, and attention to detail.

Responsibilities

• Perform tiling and layer manipulation on physical IC designs.
• Verify designs using automated Design Rule Checker (DRC).
• Ensure die-name conventions and bow measurements meet specs.
• Confirm correct layer usage and avoid forbidden layers in designs.
• Assess maturity of designs with tape-out maturity index check.
• Create stress distribution plots and align results with Process Engineer.
• Coordinate verification with Technology Team and Design Engineer.
• Advise Design Engineers on how to resolve verification errors.
• Ensure quality of final physical IC design before handing to Mask Data Preparation.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.

Skills

Electrical engineering

Semiconductor industry

Linux

AI automation

Python scripting

English communication

Problem solving

Cross-functional communication

Time management

Education

Bachelor’s degree in Electrical Engineering

Tools

Synopsys

Cadence

Klayout

Python

Linux scripting

Job description

Ampleon is seeking a Sr. Engineer, Chip Finishing to join the EST, Design Enablement team. You will work in the Philippines under the Principal Engineer, Design Enablement Team Lead, contributing to tile manipulation, DRC validation, and die‑bow checks.

You will coordinate with Design Engineers and Technology teams, ensure design quality for handoff to Mask Data Preparation, and help maintain process-flow documentation while supporting cross‑regional collaboration.