Sr Engineer Chip Finishing

Ampleon; Cabuyao; On-site; PHP 900,000 - 1,300,000; Full time

Job summary

Ampleon is seeking a Sr. Engineer, Chip Finishing to join the EST, Design Enablement team. You will work in the Philippines under the Principal Engineer, Design Enablement Team Lead, contributing to tile manipulation, DRC validation, and die‑bow checks.

You will coordinate with Design Engineers and Technology teams, ensure design quality for handoff to Mask Data Preparation, and help maintain process-flow documentation while supporting cross‑regional collaboration.

Qualifications

• Bachelor’s degree in electrical engineering or related field.
• 5 years of experience in semiconductor industry, preferably IC design.
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain root causes of violations in physical IC design.
• Familiarity with Linux and EDA tools (Synopsys, Cadence, Klayout).
• Scripting skills in Python, Bash or Tcl.
• Strong written and verbal English communication, problem solving, and attention to detail.

Responsibilities

• Perform tiling and layer manipulation on physical IC designs.
• Verify designs using automated Design Rule Checker (DRC).
• Ensure die-name conventions and bow measurements meet specs.
• Confirm correct layer usage and avoid forbidden layers in designs.
• Assess maturity of designs with tape-out maturity index check.
• Create stress distribution plots and align results with Process Engineer.
• Coordinate verification with Technology Team and Design Engineer.
• Advise Design Engineers on how to resolve verification errors.
• Ensure quality of final physical IC design before handing to Mask Data Preparation.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.

Skills

Electrical engineering

Semiconductor industry

Linux

AI automation

Python scripting

English communication

Problem solving

Cross-functional communication

Time management

Education

Bachelor’s degree in Electrical Engineering

Tools

Synopsys

Cadence

Klayout

Python

Linux scripting

Job description

Job Description:

You are going to be a part of the EST, Design Enablement team of Ampleon

The Enabling and Sustaining Technologies (EST), Design Enablementteam of Ampleon is based in the Netherlands. You are going to be part of the team in the Philippines where technologies and development engineering projects are coming together. The Philippines team is an experienced team with engaged and passionate people. This position reports to the Principal Engineer, Design Enablement Team Lead.

A look into the life of the Sr. Engineer, Chip Finishing at Ampleon

You will:

• Perform tiling and layer manipulation on physical IC designs.
• Verify physical IC designs using the automated Design Rule Checker (DRC).
• Verify that die names comply with the die-naming convention.
• Verify that die bow measurements are within the specified limits.
• Ensure that all required layers are used and that no forbidden layers are included in the physical IC design.
• Assess the maturity of physical IC designs by performing the automated tape-out maturity index check.
• Create stress distribution plots and align the results with the Process Engineer.
• Align verification errors with the Technology Team and/or Design Engineer.
• Advise the Design Engineers on how to resolve verification errors.
• Ensure the right quality of the final physical IC design before handing it over to the Mask Data Preparation Engineer.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.

We are looking for someone who has the following background and capabilities:

• Bachelor’s degree in electrical engineering or related field (Master’s degree is an advantage but not required).
• 5 years of experience in semiconductor industry (preferably related to IC design).
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain the root cause of violations in physical IC design.
• Familiarity with working in a Linux operating system.
• Familiarity with EDA tools like Synopsys, Cadence and/or Klayout.
• Familiarity with scripting languages such as Python, Bash, or Tcl.
• Strong written and verbal English communication skills.
• Strong problem-solving and analytical skills.
• Attention to detail and commitment to quality.
• Effective cross-functional communication.
• Flexibility in working hours to cover time differences between regions (CET time).
• Ability to manage multiple priorities in a fast-paced environment.
• Continuous improvement mindset.