Senior Chip Finishing Engineer — AI-Driven IC Design

Ampleon; Cabuyao; On-site; PHP 600,000 - 1,000,000; Full time

Job summary

Ampleon in Cabuyao, Philippines, is seeking a skilled IC Design Enablement Engineer to perform tiling, verification, and rule-checking on physical IC designs. You will ensure die naming, bow limits, and layer usage while supporting tape-out maturity checks and process documentation.

The role requires 5 years in semiconductors (IC design preferred), strong English communication, Linux proficiency, and experience with Synopsys, Cadence, or Klayout, plus scripting skills in Python/Bash/Tcl.

Qualifications

• Bachelor’s degree in electrical engineering or related field (Master’s degree is an advantage but not required).
• 5 years of experience in semiconductor industry (preferably related to IC design).
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain the root cause of violations in physical IC design.
• Familiarity with Linux operating system.
• Familiarity with EDA tools like Synopsys, Cadence and/or Klayout.
• Familiarity with scripting languages such as Python, Bash, or Tcl.
• Strong written and verbal English communication skills.
• Strong problem-solving and analytical skills.
• Attention to detail and commitment to quality.
• Effective cross-functional communication.
• Flexibility in working hours to cover time differences between regions (CET time).
• Ability to manage multiple priorities in a fast-paced environment.

Responsibilities

• Perform tiling and layer manipulation on physical IC designs.
• Verify physical IC designs using the automated Design Rule Checker (DRC).
• Verify that die names comply with the die-naming convention.
• Verify that die bow measurements are within the specified limits.
• Ensure that all required layers are used and that no forbidden layers are included in the physical IC design.
• Assess the maturity of physical IC designs by performing the automated tape-out maturity index check.
• Create stress distribution plots and align the results with the Process Engineer.
• Align verification errors with the Technology Team and/or Design Engineer.
• Advise the Design Engineers on how to resolve verification errors.
• Ensure the right quality of the final physical IC design before handing it over to the Mask Data Preparation Engineer.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.
• A position in an international environment with over 35 nationalities working in cross-functional teams across 16 sites
• Growth and learning opportunities to develop yourself in Ampleon
• A variety of inspiring events throughout the year, such as various development activities, sports and many more

Skills

AI workflows

Scripting (Python/Bash/Tcl)

Verbal & written English

Cross-functional communication

Problem-solving

Attention to detail

Multitasking

Time management

Education

Bachelor’s degree in electrical engineering or related field

Master’s degree a plus

Tools

Synopsys

Cadence

Klayout

Job description

Ampleon in Cabuyao, Philippines, is seeking a skilled IC Design Enablement Engineer to perform tiling, verification, and rule-checking on physical IC designs. You will ensure die naming, bow limits, and layer usage while supporting tape-out maturity checks and process documentation.

The role requires 5 years in semiconductors (IC design preferred), strong English communication, Linux proficiency, and experience with Synopsys, Cadence, or Klayout, plus scripting skills in Python/Bash/Tcl.