Sr. Engineer, Chip Finishing

Ampleon; Cabuyao; On-site; PHP 600,000 - 1,000,000; Full time

Job summary

Ampleon in Cabuyao, Philippines, is seeking a skilled IC Design Enablement Engineer to perform tiling, verification, and rule-checking on physical IC designs. You will ensure die naming, bow limits, and layer usage while supporting tape-out maturity checks and process documentation.

The role requires 5 years in semiconductors (IC design preferred), strong English communication, Linux proficiency, and experience with Synopsys, Cadence, or Klayout, plus scripting skills in Python/Bash/Tcl.

Qualifications

• Bachelor’s degree in electrical engineering or related field (Master’s degree is an advantage but not required).
• 5 years of experience in semiconductor industry (preferably related to IC design).
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain the root cause of violations in physical IC design.
• Familiarity with Linux operating system.
• Familiarity with EDA tools like Synopsys, Cadence and/or Klayout.
• Familiarity with scripting languages such as Python, Bash, or Tcl.
• Strong written and verbal English communication skills.
• Strong problem-solving and analytical skills.
• Attention to detail and commitment to quality.
• Effective cross-functional communication.
• Flexibility in working hours to cover time differences between regions (CET time).
• Ability to manage multiple priorities in a fast-paced environment.

Responsibilities

• Perform tiling and layer manipulation on physical IC designs.
• Verify physical IC designs using the automated Design Rule Checker (DRC).
• Verify that die names comply with the die-naming convention.
• Verify that die bow measurements are within the specified limits.
• Ensure that all required layers are used and that no forbidden layers are included in the physical IC design.
• Assess the maturity of physical IC designs by performing the automated tape-out maturity index check.
• Create stress distribution plots and align the results with the Process Engineer.
• Align verification errors with the Technology Team and/or Design Engineer.
• Advise the Design Engineers on how to resolve verification errors.
• Ensure the right quality of the final physical IC design before handing it over to the Mask Data Preparation Engineer.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.
• A position in an international environment with over 35 nationalities working in cross-functional teams across 16 sites
• Growth and learning opportunities to develop yourself in Ampleon
• A variety of inspiring events throughout the year, such as various development activities, sports and many more

Skills

AI workflows

Scripting (Python/Bash/Tcl)

Verbal & written English

Cross-functional communication

Problem-solving

Attention to detail

Multitasking

Time management

Education

Bachelor’s degree in electrical engineering or related field

Master’s degree a plus

Tools

Synopsys

Cadence

Klayout

Job description

ID343 | Permanent | Cabuyao, Philippines

Created in 2015 and headquartered in the Netherlands, Ampleon is shaped by nearly 60 years of RF Power leadership. The company envisions to advance society through innovative RF solutions based on GaN and LDMOS technologies.

Ampleon is dedicated to being the partner of choice by delivering high-quality, high-performance RF products with its world-class talent. The portfolio offers flexibility in scaling design and production for any volume and addresses applications for 5G NR infrastructure, industrial, scientific, medical, broadcast, navigation and safety radio applications.

Proven reliability, secure supply and excellent product consistency enable highest manufacturing yields for customers who benefit from Ampleon being a one-stop partner for RF power solutions. For more details, please visit www.ampleon.com.

The Enabling and Sustaining Technologies ( EST), Design Enablementteam of Ampleon is based in the Netherlands. You are going to be part of the team in the Philippines where technologies and development engineering projects are coming together. The Philippines team is an experienced team with engaged and passionate people. This position reports to the Principal Engineer, Design Enablement Team Lead.

You will:

• Perform tiling and layer manipulation on physical IC designs.
• Verify physical IC designs using the automated Design Rule Checker (DRC).
• Verify that die names comply with the die-naming convention.
• Verify that die bow measurements are within the specified limits.
• Ensure that all required layers are used and that no forbidden layers are included in the physical IC design.
• Assess the maturity of physical IC designs by performing the automated tape-out maturity index check.
• Create stress distribution plots and align the results with the Process Engineer.
• Align verification errors with the Technology Team and/or Design Engineer.
• Advise the Design Engineers on how to resolve verification errors.
• Ensure the right quality of the final physical IC design before handing it over to the Mask Data Preparation Engineer.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.
• A position in an international environment with over 35 nationalities working in cross-functional teams across 16 sites
• Growth and learning opportunities to develop yourself in Ampleon
• A variety of inspiring events throughout the year, such as various development activities, sports and many more

We are looking for someone who has the following background and capabilities:

• Bachelor’s degree in electrical engineering or related field (Master’s degree is an advantage but not required).
• 5 years of experience in semiconductor industry (preferably related to IC design).
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain the root cause of violations in physical IC design.
• Familiarity with working in a Linux operating system.
• Familiarity with EDA tools like Synopsys, Cadence and/or Klayout.
• Familiarity with scripting languages such as Python, Bash, or Tcl.
• Strong written and verbal English communication skills.
• Strong problem-solving and analytical skills.
• Attention to detail and commitment to quality.
• Effective cross-functional communication.
• Flexibility in working hours to cover time differences between regions (CET time).
• Ability to manage multiple priorities in a fast-paced environment.