Mid/Senior Verification Engineer

microTECH Global Limited; España; Presencial; EUR 50.000 - 70.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible work schedules

Competitive pay

Free Spanish lessons

Visa sponsorship if required

Descripción de la vacante

A leading technology firm in Barcelona is looking for a Mid/Senior Verification Engineer. The role involves ensuring the correctness of complex digital designs within the Verification Team using advanced methodologies. Candidates should have a Master or PhD, 8+ years of industrial experience, and proficiency in SystemVerilog and UVM. Flexible schedules, competitive pay, and a supportive learning environment are part of the offer. Join us and enjoy some unique perks, including free Spanish lessons.

Formación

• Industrial experience of 8+ years required.
• English proficiency at C1 level.
• Experience in block level and sub-system verification.

Responsabilidades

• Work in Verification Team ensuring the correctness of complex digital designs.
• Use advanced verification methodologies and tools.
• Validate designs at the Register Transfer Level according to specifications.

Conocimientos

Proficiency in SystemVerilog

Proficiency in UVM

Knowledge of Python

Knowledge of Perl

Knowledge of Bash

Knowledge of TCL

Strong problem-solving skills

Excellent communication skills

Excellent teamwork abilities

Educación

Master or PhD

Herramientas

Simulation tools

Regression tools

Git

SVN

Descripción del empleo

Mid/Senior Verification Engineer

Place: Barcelona, Spain

Permanent

Description

We are hiring! Are you passionate about microprocessor architecture? We need you! As a Senior Verification Engineer, you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the specification, using advanced verification methodologies and tools to validate the designs.

What we offer?

Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona. Candies, coffee and free Spanish lessons included (Visa sponsorship if required)

Requirements

• Master or PhD
• English C1
• Industrial experience +8 years
• Proficiency in SystemVerilog and UVM
• Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
• Experience with simulation and simulation tools
• Knowledge of revision control methodology and tools (git, svn)
• Experience in block level and sub-system or top-level verification
• Experience with formal and dynamic verification
• Strong problem-solving skills and attention to detail
• Excellent communication and teamwork abilities

If you would like to learn more, please email [e-mail] directly.