Design Verification Intern: Learn Tools & Verify Designs

University of St. La Salle; Cavite City; On-site; Full time

Job description

The Engineering Enablement team seeks an intern to support Systems Verification, Implementation, and Validation by applying design verification concepts and enabling verification tools.

Your Role

Here’s what you will be doing:

• Learn design verification concepts and tools.
• Apply verification by verifying a design.
• Learn about enablement of verification tools and methodologies.
• Support design verification teams.
• Work on one or more areas of enablement and support within the SVIV team.

About You

The company is looking for:

• Enrolled in BS Degree program majoring in Electronics Engineering, Computer Engineering, Electrical Engineering, or related field.
• Completed Electronics Theory and Digital Electronics courses.
• Basic knowledge of programming, circuit design, and analysis.
• Good debugging skills.
• Strong English communication skills, verbal and written.
• Good interpersonal skills.
• Knowledge of programming languages like C/C++, Verilog/SystemVerilog is an advantage.
• Knowledge of scripting languages like Perl, Python, and shell scripting is an advantage.