Lead Coherency Verification Engineer

microTECH Global Limited; España; Presencial; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible work schedules

Competitive pay

Free Spanish lessons

Candies and coffee

Descripción de la vacante

A leading technology firm in Barcelona is seeking a Lead Coherency Verification Engineer with strong expertise in SystemVerilog and UVM. The role involves ensuring the correctness of complex digital designs and requires a Master's or PhD, along with 8+ years of industrial experience. The company offers flexible schedules, competitive pay, and various perks, including free Spanish lessons. Join us to advance in a dynamic environment!

Formación

• 8+ years of industrial experience in verification.
• Fluency in English (C1 level).
• Experience with formal and dynamic verification.
• Knowledge of caches' structure and parameters.

Responsabilidades

• Ensure correctness and functionality of complex digital designs.
• Use advanced verification methodologies and tools.
• Validate designs at the Register Transfer Level according to specification.

Conocimientos

Proficiency in SystemVerilog

Proficiency in UVM

Knowledge of scripting languages

Strong problem-solving skills

Excellent communication skills

Experience in block level verification

Attention to detail

Knowledge of the CHI protocol

Educación

Master or PhD

Herramientas

SystemVerilog

UVM

Git

SVN

Regression tools

Simulation tools

Scripting languages (Python, Perl, Bash, TCL)

Descripción del empleo

Lead Coherency Verification Engineer

Place: Barcelona, Spain

Permanent

Description

We are hiring! Are you passionate about microprocessor architecture? We need you! As a Coherency Verification Engineer, you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the specification, using advanced verification methodologies and tools to validate the designs.

What do we offer?

Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona. Candies, coffee and free Spanish lessons included (Visa sponsorship if required)

Requirements

• Master or PhD
• English C1
• Industrial experience +8 years
• Proficiency in SystemVerilog and UVM
• Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
• Experience with simulation and simulation tools
• Knowledge of revision control methodology and tools (git, svn)
• Experience in block level and sub-system or top-level verification
• Experience with formal and dynamic verification
• Strong problem-solving skills and attention to detail
• Excellent communication and teamwork abilities
• Knowledge of the CHI protocol
• Understanding of caches' structure and parameters
• Experience in verification of coherent systems

If you would like to learn more, please email [e-mail] directly.