Senior Chip Finishing Engineer - AI-Driven IC QA

AMPLEON PHILIPPINES, INC.; Laguna; On-site; PHP 900,000 - 1,100,000; Full time

Benefits offered by this job

International environment

Growth opportunities

Professional events

Job summary

Ampleon Philippines, Inc. is seeking a Sr. Engineer, Chip Finishing to join the EST, Design Enablement team in the Philippines. You will perform tiling, layer manipulation, and verification of physical IC designs, collaborating with the Tech team to resolve violations and ensure design quality.

The role requires 5 years in semiconductors, AI and automation experience, strong Linux and scripting skills, and effective cross-functional communication across regions. CET hours flexibility.

Qualifications

• Bachelor's degree in electrical engineering or related field.
• 5 years of experience in semiconductor industry (preferably IC design).
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain root cause of violations in physical IC design.
• Familiarity with Linux operating system.
• Familiarity with EDA tools like Synopsys, Cadence and/or Klayout.
• Familiarity with scripting languages such as Python, Bash, or Tcl.
• Strong written and verbal English communication skills.
• Strong problem-solving and analytical skills.
• Attention to detail and commitment to quality.
• Effective cross-functional communication.
• Flexibility in working hours to cover time differences (CET).
• Ability to manage multiple priorities in a fast-paced environment.
• Continuous improvement mindset.

Responsibilities

• Perform tiling and layer manipulation on physical IC designs.
• Verify physical IC designs using the automated Design Rule Checker (DRC).
• Verify that die names comply with the die-naming convention.
• Verify that die bow measurements are within the specified limits.
• Ensure that all required layers are used and that no forbidden layers are included.
• Assess the maturity of physical IC designs by automated tape-out maturity index check.
• Create stress distribution plots and align results with the Process Engineer.
• Align verification errors with the Technology Team and/or Design Engineer.
• Advise the Design Engineers on how to resolve verification errors.
• Ensure the right quality of the final physical IC design before handing to Mask Data Preparation Engineer.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.

Skills

AI automation

Linux

Scripting (Python, Bash, Tcl)

English communication

Education

Bachelors in Electrical Engineering

Tools

Synopsys

Cadence

Klayout

Job description

Ampleon Philippines, Inc. is seeking a Sr. Engineer, Chip Finishing to join the EST, Design Enablement team in the Philippines. You will perform tiling, layer manipulation, and verification of physical IC designs, collaborating with the Tech team to resolve violations and ensure design quality.

The role requires 5 years in semiconductors, AI and automation experience, strong Linux and scripting skills, and effective cross-functional communication across regions. CET hours flexibility.