Senior Engineer Chip Finishing

AMPLEON PHILIPPINES, INC.; Laguna; Vor Ort; PHP 900.000 - 1.100.000; Vollzeit

Benefits dieser Stelle

International environment

Growth opportunities

Professional events

Zusammenfassung

Ampleon Philippines, Inc. is seeking a Sr. Engineer, Chip Finishing to join the EST, Design Enablement team in the Philippines. You will perform tiling, layer manipulation, and verification of physical IC designs, collaborating with the Tech team to resolve violations and ensure design quality.

The role requires 5 years in semiconductors, AI and automation experience, strong Linux and scripting skills, and effective cross-functional communication across regions. CET hours flexibility.

Qualifikationen

• Bachelor's degree in electrical engineering or related field.
• 5 years of experience in semiconductor industry (preferably IC design).
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain root cause of violations in physical IC design.
• Familiarity with Linux operating system.
• Familiarity with EDA tools like Synopsys, Cadence and/or Klayout.
• Familiarity with scripting languages such as Python, Bash, or Tcl.
• Strong written and verbal English communication skills.
• Strong problem-solving and analytical skills.
• Attention to detail and commitment to quality.
• Effective cross-functional communication.
• Flexibility in working hours to cover time differences (CET).
• Ability to manage multiple priorities in a fast-paced environment.
• Continuous improvement mindset.

Aufgaben

• Perform tiling and layer manipulation on physical IC designs.
• Verify physical IC designs using the automated Design Rule Checker (DRC).
• Verify that die names comply with the die-naming convention.
• Verify that die bow measurements are within the specified limits.
• Ensure that all required layers are used and that no forbidden layers are included.
• Assess the maturity of physical IC designs by automated tape-out maturity index check.
• Create stress distribution plots and align results with the Process Engineer.
• Align verification errors with the Technology Team and/or Design Engineer.
• Advise the Design Engineers on how to resolve verification errors.
• Ensure the right quality of the final physical IC design before handing to Mask Data Preparation Engineer.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.

Kenntnisse

AI automation

Linux

Scripting (Python, Bash, Tcl)

English communication

Ausbildung

Bachelors in Electrical Engineering

Tools

Synopsys

Cadence

Klayout

Jobbeschreibung

About the Role

The Enabling and Sustaining Technologies (EST), Design Enablementteam of Ampleon is based in the Netherlands. You are going to be part of the team in the Philippines where technologies and development engineering projects are coming together. The Philippines team is an experienced team with engaged and passionate people. This position reports to the Principal Engineer, Design Enablement Team Lead.

Company Description

Advancing society through RF. Join Ampleon!

Created in 2015 and headquartered in the Netherlands, Ampleon is shaped by nearly 60 years of RF Power leadership. The company envisions to advance society through innovative RF solutions based on GaN and LDMOS technologies.

Ampleon is dedicated to being the partner of choice by delivering high-quality, high-performance RF products with its world-class talent. The portfolio offers flexibility in scaling design and production for any volume and addresses applications for 5G NR infrastructure, industrial, scientific, medical, broadcast, navigation and safety radio applications.

Proven reliability, secure supply and excellent product consistency enable highest manufacturing yields for customers who benefit from Ampleon being a one-stop partner for RF power solutions. For more details, please visit www.ampleon.com.

You will (Key Reponsibilities):

A look into the life of the Sr. Engineer, Chip Finishing at Ampleon

• Perform tiling and layer manipulation on physical IC designs.
• Verify physical IC designs using the automated Design Rule Checker (DRC).
• Verify that die names comply with the die-naming convention.
• Verify that die bow measurements are within the specified limits.
• Ensure that all required layers are used and that no forbidden layers are included in the physical IC design.
• Assess the maturity of physical IC designs by performing the automated tape-out maturity index check.
• Create stress distribution plots and align the results with the Process Engineer.
• Align verification errors with the Technology Team and/or Design Engineer.
• Advise the Design Engineers on how to resolve verification errors.
• Ensure the right quality of the final physical IC design before handing it over to the Mask Data Preparation Engineer.
• Present chip-finishing results to the Project Team.
• Maintain process-flow documentation and tools.

Your profile (Qualifications)

We are looking for someone who has the following background and capabilities:

• Bachelor's degree in electrical engineering or related field (Master's degree is an advantage but not required).
• 5 years of experience in semiconductor industry (preferably related to IC design).
• Experience with AI and automating flows is a must.
• Understanding of semiconductor technology design rules.
• Ability to explain the root cause of violations in physical IC design.
• Familiarity with working in a Linux operating system.
• Familiarity with EDA tools like Synopsys, Cadence and/or Klayout.
• Familiarity with scripting languages such as Python, Bash, or Tcl.
• Strong written and verbal English communication skills.
• Strong problem-solving and analytical skills.
• Attention to detail and commitment to quality.
• Effective cross-functional communication.
• Flexibility in working hours to cover time differences between regions (CET time).
• Ability to manage multiple priorities in a fast-paced environment.
• Continuous improvement mindset.

We offer you

• A position in an international environment with over 35 nationalities working in cross-functional teams across 16 sites
• Growth and learning opportunities to develop yourself in Ampleon
• A variety of inspiring events throughout the year, such as various development activities, sports and many more