Senior Physical Design Engineer: ML-Driven RTL-to-GDS

SiFive, Inc.; Hinoba-an; On-site; PHP 1,653,000 - 2,975,000; Full time

Job summary

SiFive, Inc. in India seeks a Senior Physical Design Engineer to own the RTL-to-GDS flow for high-performance CPU cores. You will drive block-level implementation and PPA closure on N3/N5 FinFET nodes, delivering reliable, repeatable results in a collaborative, fast-moving team.

You will apply Synopsys Fusion Compiler, ICC2, PrimeTime and ML-enhanced methods to reach aggressive frequency and power targets, with Tcl/Python scripting to automate flows and improve efficiency.

Qualifications

• 3+ years of hands-on experience in Physical Design/Methodology.
• Strong experience with FinFET nodes (N5/N3); familiarity with N2/GAAFET is a plus.
• Deep knowledge of Synopsys digital implementation suite and design flows.

Responsibilities

• Flow Execution & Validation: implement, validate, and maintain RTL-to-GDS recipes using Fusion Compiler.
• Block Ownership: own medium-sized CPU sub-block implementations from RTL to GDS sign-off.
• PPA Optimization: drive block-level PPA closure and timing-driven placement/routing.
• ML Deployment: leverage ML tools to optimize design space and target performance.

Skills

Physical design

RTL-to-GDS

PPA optimization

Python/Tcl scripting

Team collaboration

Tools

Fusion Compiler

ICC2

PrimeTime

StarRC

Python

Tcl

Job description

SiFive, Inc. in India seeks a Senior Physical Design Engineer to own the RTL-to-GDS flow for high-performance CPU cores. You will drive block-level implementation and PPA closure on N3/N5 FinFET nodes, delivering reliable, repeatable results in a collaborative, fast-moving team.

You will apply Synopsys Fusion Compiler, ICC2, PrimeTime and ML-enhanced methods to reach aggressive frequency and power targets, with Tcl/Python scripting to automate flows and improve efficiency.