Senior Physical Design Engineer, Interconnects (NoC)

SiFive, Inc.; Hinoba-an; On-site; PHP 7,505,000 - 11,257,000; Full time

Job summary

SiFive is seeking a Senior Physical Design Engineer (Interconnects) to lead RTL-to-GDSII implementation of high-speed NoC and memory interconnects for modern SoCs. You will tackle floorplanning, timing closure, and global clock distribution, bridging RTL and physical design on 7nm or below nodes.

Bring 4+ years in physical design, strong NoC knowledge, MMMC timing closure, and proficiency with Synopsys/Cadence flows.

Qualifications

• BS or MS in Electrical or Computer Engineering or related field.
• 4+ years of hands-on physical design experience on high-speed interconnects.
• Experience closing blocks in FinFET nodes (7nm or below).
• Familiarity with RTL-to-GDSII flows and CPU/GPU interconnects is a plus.

Responsibilities

• Own RTL-to-GDSII implementation of System IP components (NoC fabrics, coherent clusters, memory subsystems).
• Collaborate with design/architecture to resolve physical bottlenecks via microarchitectural tweaks or pipelining.
• Develop and refine floorplans for large bus-heavy subsystems.
• Close timing on wide, high-frequency buses and manage global clock distribution.

Skills

RTL reading

NoC architectures

Coherent interconnects

Timing closure

MMMC timing

Data-driven optimization

Education

BS or MS in Electrical/Computer Engineering

Tools

Synopsys tools

Cadence tools

Job description

SiFive is seeking a Senior Physical Design Engineer (Interconnects) to lead RTL-to-GDSII implementation of high-speed NoC and memory interconnects for modern SoCs. You will tackle floorplanning, timing closure, and global clock distribution, bridging RTL and physical design on 7nm or below nodes.

Bring 4+ years in physical design, strong NoC knowledge, MMMC timing closure, and proficiency with Synopsys/Cadence flows.