Senior ASIC Digital Implementation Lead (RTL–GDSII)

Xinyx Design Consultancy & Services, Inc.; Muntinlupa; On-site; PHP 900,000 - 1,300,000; Full time

Job summary

Xinyx Design Consultancy & Services, Inc. is seeking a Senior Digital Implementation Engineer in Metro Manila to lead end-to-end ASIC/FPGA implementation, including synthesis, place-and-route, and timing closure.

The role requires strong RTL/Verilog skills and hands-on experience with major EDA flows. You will drive optimization, mentor junior engineers, and collaborate with RTL, verification, and physical design teams to ensure design intent and timing goals are met.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field.
• 5–8 years of experience in digital design implementation, with ASIC/FPGA flows.
• Proficiency in RTL design languages and timing analysis methodologies.

Responsibilities

• Lead synthesis, place and route, and optimization of complex digital designs.
• Perform static timing analysis and drive timing closure across corners.
• Collaborate with RTL designers, verification, and physical design teams.
• Develop and improve digital implementation methodologies and flows.
• Utilize EDA tools effectively for implementation tasks and automation.
• Identify and resolve DRC/LVS and timing issues through debugging.
• Maintain documentation of design processes and deliverables.
• Provide mentorship to junior engineers in digital design implementation.

Skills

Digital design concepts

Verilog/SystemVerilog

Static timing analysis

Synthesis/Place&Route

Collaboration

Scripting (Python, Perl, Tcl)

Education

Bachelor’s in Electrical / Computer Engineering

Master's degree preferred

Tools

Synopsys Design Compiler

Cadence Innovus

Mentor Graphics

Job description

Xinyx Design Consultancy & Services, Inc. is seeking a Senior Digital Implementation Engineer in Metro Manila to lead end-to-end ASIC/FPGA implementation, including synthesis, place-and-route, and timing closure.

The role requires strong RTL/Verilog skills and hands-on experience with major EDA flows. You will drive optimization, mentor junior engineers, and collaborate with RTL, verification, and physical design teams to ensure design intent and timing goals are met.