Junior Design Verification Engineer — SystemVerilog & UVM

Analog Devices, Inc.; Luan; On-site; PHP 4,459,000 - 6,369,000; Full time

Job summary

Analog Devices, Inc. is seeking an Associate Design Verification Engineer to develop test benches and verify new digital, analog, and mixed-signal products before tape-out.

This entry-level role focuses on learning and development under close direction with regular reviews. You'll gain hands-on experience with verification methodologies and collaborate with experienced engineers who will guide your professional growth.

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, or related field.
• 0-2 years of relevant experience; new graduates are welcome to apply.
• Basic proficiency with SystemVerilog/UVM and verification workflows.

Responsibilities

• Develop and execute basic test benches for mixed-signal product verification.
• Create and maintain basic test environments using SystemVerilog/UVM.
• Conduct code coverage analysis to ensure design accuracy.
• Debug simulation failures and track coverage metrics.
• Support verification planning and documentation.
• Collaborate with design teams to understand requirements.
• Identify potential design issues under guidance of senior team members.
• Document verification processes and results.

Skills

SystemVerilog

UVM

Python

Verilog RTL

I2C

SPI

UART

Debugging

Education

Bachelor's degree in Electrical Engineering, Electronics and Communications Engineering, Computer Engineering, or related field

Job description

Analog Devices, Inc. is seeking an Associate Design Verification Engineer to develop test benches and verify new digital, analog, and mixed-signal products before tape-out.

This entry-level role focuses on learning and development under close direction with regular reviews. You'll gain hands-on experience with verification methodologies and collaborate with experienced engineers who will guide your professional growth.