Design Verification Engineer

CAI; Philippines; Remote; PHP 600,000 - 1,200,000; Full time

Job summary

CAI is a global services firm providing engineering verification expertise and digital design services. We are seeking a Design Verification Engineer to develop test benches for mixed-signal product verification, ensuring regression coverage and reliability.

This full-time remote role offers opportunities to work with cross-functional teams and apply SystemVerilog/UVM methodologies. The candidate will create and maintain verification environments, collaborate on project timelines, and contribute

Qualifications

• Bachelor’s or Master’s degree in Electrical/EC/Computer Engineering or related field.
• 2–4 years of digital design verification experience.
• Proficient in SystemVerilog and UVM for complex verification.
• Experience developing test benches for mixed-signal verification.
• Scripting in Python, Perl, or TCL for automation.
• Strong RTL understanding and Verilog concepts.
• Experience with EDA tools and simulators.
• Ability to debug verification issues with limited supervision.

Responsibilities

• Develop and execute comprehensive test benches for mixed-signal product verification using SystemVerilog and UVM methodologies.
• Create verification plans and measure functional and code coverage metrics to ensure design quality.
• Debug verification issues using advanced troubleshooting techniques and provide effective solutions.
• Collaborate with design teams to align verification strategies with project requirements.

Skills

SystemVerilog

UVM

Test benches

Python scripting

Verilog RTL

Digital verification

EDA tools

Debugging

Education

Electrical/EC Eng degree

Tools

EDA tools

Job description

Design Verification Engineer

Req number: R8709

Employment type: Full time

Worksite flexibility: Remote

Who we are

CAI is a global services firm with over 9,000 associates worldwide and a yearly revenue of $1.3 billion+. We have over 40 years of excellence in uniting talent and technology to power the possible for our clients, colleagues, and communities. As a privately held company, we have the freedom and focus to do what is right—whatever it takes. Our tailor‑made solutions create lasting results across the public and commercial sectors, and we are trailblazers in bringing neurodiversity to the enterprise.

Job Summary

As a Design Verification Engineer, you will develop test benches and perform design verification of mixed-signal products prior to tape‑out. You'll create advanced environments that support comprehensive, metric‑driven verification processes and ensure the accuracy and reliability of designs through code coverage analysis. Working with moderate supervision, you'll collaborate with cross‑functional teams to meet project timelines and quality standards, applying your technical expertise to solve verification challenges.

Job Description

We are looking for an experienced Design Verification Engineer to develop and execute comprehensive test benches for mixed‑signal product verification using SystemVerilog and UVM methodologies. This position is full‑time and remote.

What You’ll Do

• Develop and execute comprehensive test benches for mixed‑signal product verification using SystemVerilog and UVM methodologies


• Create and maintain verification plans, focusing on functional and code coverage metrics to ensure design quality


• Debug verification issues using advanced troubleshooting techniques and provide effective solutions


• Collaborate with design teams to align verification strategies with project requirements


• Create and maintain detailed documentation for verification processes and results


• Participate in design reviews and provide verification insights to improve overall product quality


• Apply scripting skills and use AI tools to automate verification tasks and improve efficiency

What You’ll Need

Required:

• Bachelor’s or Master’s degree in electrical engineering, Electronics and Communications Engineering, Computer Engineering, or related field


• 2 to 4 years of relevant experience in digital design verification


• SystemVerilog & UVM: Proficiency in developing and maintaining verification environments using SystemVerilog and Universal Verification Methodology for complex designs


• Test Bench Development: Ability to develop comprehensive test benches for mixed‑signal product verification, focusing on coverage‑driven methodologies


• Scripting: Capability to create and implement automation scripts using Python, Perl, or TCL to enhance verification workflows


• Verilog RTL: Strong understanding of Register Transfer Level design concepts and their application in verification


• EDA Tools: Experience with electronic design automation tools and simulators for effective design verification


• Debugging: Demonstrated ability to analyze and resolve moderately complex verification issues with limited supervision

Physical Demands

• Ability to safely and successfully perform the essential job functions


• Sedentary work that involves sitting or remaining stationary most of the time, with occasional need to move around the office to attend meetings, etc.


• Ability to conduct repetitive tasks on a computer, utilizing a mouse, keyboard, and monitor

Reasonable accommodation statement

If you require a reasonable accommodation in completing this application, interviewing, completing any pre‑employment testing, or otherwise participating in the employment selection process, please direct your inquiries to [e-mail] or (888) 824 – 8111.