Entry-Level Design Verification Engineer: SystemVerilog/UVM

Analog Devices; Cavite City; On-site; PHP 480,000 - 600,000; Full time

Job summary

Analog Devices, Inc. is seeking an Associate Design Verification Engineer to contribute to the verification of digital, analog and mixed-signal products prior to tape‑out. This entry-level role focuses on learning under guidance with regular reviews.

You'll gain hands-on experience with verification methodologies, collaborate with senior engineers, and develop fundamental test benches, test environments, and documentation to support product quality and on-time development.

Qualifications

• Bachelor's degree in a relevant engineering field
• 0–2 years of relevant experience; new graduates welcome
• Basic proficiency in SystemVerilog/UVM and Verilog RTL

Responsibilities

• Develop and execute basic test benches for mixed-signal product verification
• Create and maintain basic test environments using SystemVerilog/UVM
• Conduct code coverage analysis to ensure design accuracy
• Debug simulation failures and track coverage metrics
• Support verification planning and documentation
• Collaborate with design teams to understand requirements
• Identify potential design issues under guidance of senior team members
• Document verification processes and results

Skills

SystemVerilog & UVM

Python/Perl/TCL scripting

Verilog RTL

Digital interfaces I2C/SPI/UART

Simulation tools

Problem solving

Communication

Education

Bachelor's degree in Electrical Engineering / Electronics and Communications Engineering / Computer Engineering

0-2 years of relevant experience; new graduates welcome

Job description

Analog Devices, Inc. is seeking an Associate Design Verification Engineer to contribute to the verification of digital, analog and mixed-signal products prior to tape‑out. This entry-level role focuses on learning under guidance with regular reviews.

You'll gain hands-on experience with verification methodologies, collaborate with senior engineers, and develop fundamental test benches, test environments, and documentation to support product quality and on-time development.