Junior Design Verification Engineer - SystemVerilog/UVM

Analog Devices, Inc.; Philippines; Hybrid; PHP 240,000 - 480,000; Full time

Job summary

Analog Devices, Inc. in the Philippines is seeking an Associate Design Verification Engineer.

This entry-level role emphasizes learning and development, with responsibilities to develop test benches for mixed-signal products and build basic environments using SystemVerilog/UVM under close supervision. You will gain hands-on experience in verification methodologies and tools, collaborating with senior engineers who guide your growth, and contribute to verification planning, documentation, and

Qualifications

• SystemVerilog/UVM knowledge for basic test environments.
• Python/Perl/TCL scripting for automation tasks.
• Verilog RTL fundamentals and digital design concepts.
• Familiarity with I2C, SPI, UART protocols.
• Ability to debug simulations and analyze coverage.

Responsibilities

• Develop and execute basic test benches for mixed-signal verification.
• Create and maintain basic test environments using SystemVerilog/UVM.
• Conduct code coverage analysis to ensure design accuracy.
• Debug simulation failures and track coverage metrics.
• Support verification planning and documentation.
• Collaborate with design teams to understand requirements.
• Identify potential design issues under guidance of senior team members.
• Document verification processes and results.

Skills

SystemVerilog/UVM

Python/Perl/TCL

Verilog RTL

Digital interfaces (I2C/SPI/UART)

Simulation tools

Problem solving

Communication

Education

Bachelor's degree in Electrical/Electronics and Communications/Computer Engineering or related field

Tools

Waveform debugging tools

Verilog/SystemVerilog simulators

Job description

Analog Devices, Inc. in the Philippines is seeking an Associate Design Verification Engineer.

This entry-level role emphasizes learning and development, with responsibilities to develop test benches for mixed-signal products and build basic environments using SystemVerilog/UVM under close supervision. You will gain hands-on experience in verification methodologies and tools, collaborating with senior engineers who guide your growth, and contribute to verification planning, documentation, and