Senior Formal Verification Engineer – RISC-V/Chisel

SiFive, Inc.; Hinoba-an; On-site; PHP 7,509,000 - 11,890,000; Full time

Job summary

SiFive is seeking a senior Formal Verification engineer to identify blocks for formal verification, design test plans, and maintain FV environments. You will apply formal techniques to prove correctness of DUT, debug RTL, and mentor teammates in FV tool usage.

The role requires leading verification efforts across blocks and improving assertion libraries. Ideal candidates have 7+ years in Formal Verification, with BS/MS/PhD in EE/CE/CS or related field, and familiarity with VC Formal/JasperGold

Qualifications

• 7+ years of experience in Formal Verification of Digital Hardware Design.
• BS/MS/PhD in EE/CE/CS or related field.
• Extensive experience with Formal Abstraction Techniques and sign-off process.
• Familiarity with Formal Verification Tools such as VC Formal and JasperGold.
• Knowledge of Verilog, SystemVerilog and VHDL.

Responsibilities

• Identify blocks suitable for applying Formal Verification.
• Create Formal Test-plans for blocks with properties and sign-off metrics.
• Implement and maintain Formal Verification environments in Chisel.
• Apply FV techniques to reduce complexity and prove DUT correctness.
• Debug RTL to identify failure scenarios.
• Guide and train team members on FV tools usage.
• Develop/modify scripts to automate verification processes.
• Review formal setups and proofs with design and verification teams.
• Maintain and extend assertion libraries.

Skills

Formal Verification

Hardware Design

Verilog/SystemVerilog

VHDL

Object-oriented programming

Teamwork

Education

BS/MS/PhD in EE/CE/CS or related field

Tools

VC Formal

JasperGold

Verilog

SystemVerilog

VHDL

Job description

SiFive is seeking a senior Formal Verification engineer to identify blocks for formal verification, design test plans, and maintain FV environments. You will apply formal techniques to prove correctness of DUT, debug RTL, and mentor teammates in FV tool usage.

The role requires leading verification efforts across blocks and improving assertion libraries. Ideal candidates have 7+ years in Formal Verification, with BS/MS/PhD in EE/CE/CS or related field, and familiarity with VC Formal/JasperGold