Senior DFT Engineer for SoC RTL & Silicon Validation

Arm Limited; Hinoba-an; Hybrid; PHP 1,200,000 - 1,300,000; Full time

Job summary

Arm Limited is seeking a DFT engineer to architect and implement innovative DFT techniques for ARM-based SoCs. You will insert DFT logic at RTL and gate levels, validate features, and generate ATE-targeted test patterns for silicon validation.

You’ll work closely with front-end design, back-end, and Test teams to achieve timing closure and robust silicon characterization. A degree in Electronic/Computer Engineering is required, with 3–20 years of related experience.

Qualifications

• Experience with DFT techniques for ARM/SoC architectures.
• 3–20 years of overall experience in electronics/ASIC verification.
• Strong Verilog RTL, TCL and Perl coding skills.

Responsibilities

• Architect, implement, and validate DFT techniques on ARM SoCs.
• Insert DFT logic at RTL and gate levels; validate features and generate ATE test patterns.
• Collaborate with front-end and back-end teams for timing closure and silicon validation.

Skills

Scan compression & insertion

Memory BIST & repair

Logic BIST

JTAG/IJTAG

ATPG

Fault simulation

Verilog RTL coding

TCL scripting

Perl scripting

Unix/Linux proficiency

Education

Bachelor’s or Master’s degree in Electronic/Computer Engineering or related field

Tools

Siemens DFT tools

Cadence tools

Synopsys DFT & simulation tools

Job description

Arm Limited is seeking a DFT engineer to architect and implement innovative DFT techniques for ARM-based SoCs. You will insert DFT logic at RTL and gate levels, validate features, and generate ATE-targeted test patterns for silicon validation.

You’ll work closely with front-end design, back-end, and Test teams to achieve timing closure and robust silicon characterization. A degree in Electronic/Computer Engineering is required, with 3–20 years of related experience.