Lead AI-Enabled RISC-V CPU IP Design Engineer

GlobalFoundries inc.; Hinoba-an; On-site; PHP 1,200,000 - 1,800,000; Full time

Job summary

GlobalFoundries Inc. in the Philippines is seeking an experienced CPU IP Design Engineer to lead RTL development for a new AI-enabled RISC-V CPU core.

You will own functional features, performance, power and area goals across the design lifecycle. Key responsibilities include micro-architecture definition, vector CPU core and extensions, RTL development, verification strategy, and collaboration with cross-functional teams to ensure timing, area and reliability targets are met in a demanding SoC

Qualifications

• Hands-on knowledge of CPU pipeline stages (in-order or out-of-order).
• Strong understanding of microprocessor architecture and RTL design basics.
• Experience with simulators and waveform debugging tools.
• Master's degree with 4–7 years experience; PhD 2–5 years is advantageous.

Responsibilities

• Drive micro-architecture and design of critical CPU blocks.
• Design RISC-V Vector CPU core and custom extensions.
• Design AI-enabled Matrix engine to augment the Vector CPU.
• Explore high-performance strategies with the CPU modeling team.
• Support verification strategy and RTL performance goals.
• Collaborate with multi-functional teams for timing, area and power.

Skills

CPU architecture knowledge

RTL design

SystemVerilog/VHDL

Verification methodology

Scripting (Python/Perl)

CPU microarchitecture experience

Education

Master's degree in a related field

PhD (preferred)

Tools

Verilog/SystemVerilog tools

VHDL simulators

Job description

GlobalFoundries Inc. in the Philippines is seeking an experienced CPU IP Design Engineer to lead RTL development for a new AI-enabled RISC-V CPU core.

You will own functional features, performance, power and area goals across the design lifecycle. Key responsibilities include micro-architecture definition, vector CPU core and extensions, RTL development, verification strategy, and collaboration with cross-functional teams to ensure timing, area and reliability targets are met in a demanding SoC