Entry-Level RISC-V Physical Design Engineer

SiFive, Inc.; Hinoba-an; On-site; PHP 400,000 - 540,000; Full time

Job summary

SiFive, Inc. is seeking an entry-level Physical Design Engineer to jump-start your career on high-performance CPUs across RTL to GDSII.

You will learn the end-to-end ASIC design flow while collaborating with veterans to translate architectural decisions into physical realizations. You will be trained to operate across design-abstraction layers, understand the impact of pipeline, datapath, and control logic on power, performance, and area, and contribute to real-world products on advanced process

Qualifications

• Strong academic foundation in computer architecture and digital design.
• Experience with RTL (Verilog/SystemVerilog) and digital logic.
• Willingness to learn EDA tools (Synopsys or Cadence) and end-to-end flow.
• Strong scripting ability (Python/Tcl/Bash) to automate workflows.

Responsibilities

• Assist physical design flow: synthesis, place & route, timing closure.
• Bridge architecture and RTL awareness across design layers.
• Analyze timing, routing, and power; support PPA goals.
• Develop scripts to automate workflows.
• Collaborate with RTL, microarchitecture, and methodology teams.

Skills

Digital design

RTL/Verilog

Scripting

EDA tools

Computer architecture

Team collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Job description

SiFive, Inc. is seeking an entry-level Physical Design Engineer to jump-start your career on high-performance CPUs across RTL to GDSII.

You will learn the end-to-end ASIC design flow while collaborating with veterans to translate architectural decisions into physical realizations. You will be trained to operate across design-abstraction layers, understand the impact of pipeline, datapath, and control logic on power, performance, and area, and contribute to real-world products on advanced process