Digital Design Verification Engineer

Cis Electronics Engineering; España; On-site; EUR 60,000 - 90,000; Full time

Job summary

Cis Electronics Engineering is seeking a Digital Design Verification Engineer for Gasteiz / Vitoria, Spain, with freelance/remote options. The candidate will lead SystemVerilog/UVM based verification for complex SoCs and work across teams to ensure robust coverage and validation results.

Strong experience in constrained-random verification is required, along with scripting skills (Python/Perl/TCL) for regression automation and remote collaboration capabilities in English.

Qualifications

• Proven hands-on experience in ASIC/FPGA digital design verification for complex mixed-signal or processor-based SoCs.
• Deep expertise in SystemVerilog and UVM testbench development.
• Strong background in constrained-random verification and functional/code coverage closure.

Responsibilities

• Verify ASIC/FPGA designs using SystemVerilog and UVM and develop verification plans.
• Execute regression flows and automate tests using Python, Perl or TCL.
• Collaborate with design teams to ensure coverage closure and quality targets.

Skills

SystemVerilog

UVM

Digital design verification

Constrained-random verification

Functional coverage

Code coverage

Python

Perl

TCL

EDA tools

Tools

EDA tools

Job description

Digital Design Verification Engineer Cis Electronics Engineering Gasteiz / Vitoria, Spain

Digital Design Verification Engineer (Freelance / Remote)Location: Remote (ideally based in Europe)Project Type: Freelance / ContractRequired Skills & ExperienceProven hands-on experience in ASIC/FPGA digital design verification for complex mixed-signal or processor-based SoCs.Deep expertise in SystemVerilog and UVM (Universal Verification Methodology) testbench development.Strong background in constrained-random verification and functional/code coverage closure.Proficiency in creating and executing verification plans.Hands-on experience with standard EDA simulation tools.Strong scripting skills in Python, Perl, or TCL for regression flows and automation. xqziphu Excellent remote communication and collaboration skills in English.

Digital Design Verification Engineer Gasteiz / Vitoria, Spain