Senior Verification Engineer, Mixed-Signal CMOS (SV/UVM)

European Tech Recruit; Den Haag; On-site; EUR 90,000 - 120,000; Full time

Job summary

European Tech Recruit is seeking an experienced Verification Engineer to join a market-leading semiconductor company in Delft, The Netherlands. You will develop SV-RNM models, create verification plans, and drive tape-out readiness.

The role requires 6 years of verification in semiconductors, strong SystemVerilog/SVA skills, and Cadence Virtuoso experience. You will collaborate with dispersed teams across design and test disciplines; visa/relocation support available.

Qualifications

• Bachelor's degree in electrical/computer engineering or related field.
• Minimum 6 years of verification experience in the semiconductor industry.
• Proficient in SystemVerilog and SystemVerilog OOP.
• Experience with UVM-based verification environments.
• Fluency with Perl and Python scripting.
• Knowledge of SystemVerilog Assertions (SVA) is essential.
• Familiarity with analog/mixed-signal verification and Cadence Virtuoso.

Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits.
• Create verification plans from chip or block specifications.
• Define and write SystemVerilog Assertions (SVA).
• Define and write functional coverages and covergroups.
• Run simulations and debug results.
• Review verification results for tape-out sign-off.
• Collaborate with design/test/verification stakeholders across dispersed teams.

Skills

SystemVerilog

UVM

SVA

Perl / Python

Cadence Virtuoso

Verilog

Tape-out

Scripting

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Cadence Virtuoso

SystemVerilog Simulators

Job description

European Tech Recruit is seeking an experienced Verification Engineer to join a market-leading semiconductor company in Delft, The Netherlands. You will develop SV-RNM models, create verification plans, and drive tape-out readiness.

The role requires 6 years of verification in semiconductors, strong SystemVerilog/SVA skills, and Cadence Virtuoso experience. You will collaborate with dispersed teams across design and test disciplines; visa/relocation support available.