Staff Digital Design Engineer

Jobtailor; Rijswijk; On-site; EUR 120,000 - 180,000; Full time

Job summary

Jobtailor is seeking an experienced ASIC digital design architect to lead front-end design of neuromorphic SoCs. You will translate high-level requirements into RTL-level specifications and microarchitectures, and own SystemVerilog/Verilog coding, simulation, synthesis, STA and design documentation.

You will collaborate with the verification team, draft timing constraints, integrate third-party IP, mentor junior engineers, and drive low-power optimizations across the full SoC bring-up.

Qualifications

• 7+ years of hands-on ASIC digital design experience focusing on complex IP blocks and SoC integration.
• Strong RTL design and debugging skills in SystemVerilog/Verilog.
• Deep understanding of SoC architecture, memory-mapped bus interfaces, and IP integration flows.
• Experience with Cadence tools and EDA flows.
• Proven ability to define PPA goals, perform synthesis and static timing analysis.
• Familiarity with DFT, gate-level simulations, and low-power design methodologies.
• Comfortable drafting specifications, design documents, and reviewing HW/SW integration requirements.
• Exposure to functional verification and writing or reviewing testbenches.

Responsibilities

• Architect, design, and implement digital IP blocks and subsystems for neuromorphic SoCs.
• Translate high-level product and algorithmic requirements into RTL-level specifications and microarchitectures.
• Own front-end design activities including RTL coding (SystemVerilog/Verilog), simulation, synthesis, STA, and design documentation.
• Collaborate with the verification team to review test plans and co‑develop functional testbenches.
• Draft timing constraints and interface closely with backend engineers during physical design and gate‑level simulation.
• Integrate third‑party IP and contribute to SoC‑level architecture and bring‑up.
• Apply low‑power design techniques and optimize for PPA.
• Work with cross‑functional teams including algorithm, platform/firmware, applications, and analog design.
• Mentor more junior engineers, contribute to code reviews, and elevate overall team's expertise

Skills

SystemVerilog/Verilog

ASIC digital design

SoC architecture

Cadence tools

Synthesis & STA

Low-power design

DFT

Testbench development

RTL debugging

Mentoring

Job description

• Architect, design, and implement digital IP blocks and subsystems for our neuromorphic SoCs
• Translate high-level product and algorithmic requirements into RTL-level specifications and microarchitectures
• Own all front-end design activities including RTL coding (SystemVerilog/Verilog), simulation, synthesis, STA, and design documentation
• Collaborate with the verification team to review test plans and co‑develop functional testbenches
• Draft timing constraints and interface closely with backend engineers during physical design and gate‑level simulation
• Integrate third‑party IP and contribute to SoC‑level architecture and bring‑up
• Apply low‑power design techniques and optimize for PPA
• Work with cross‑functional teams including algorithm, platform/firmware, applications, and analog design
• Mentor more junior engineers, contribute to code reviews, and elevate overall team's expertise

Requirements

• 7+ years of hands‑on experience in ASIC digital design, with a focus on complex IP blocks and SoC-level integration
• Strong RTL design and debugging skills in SystemVerilog/Verilog
• Deep understanding of SoC architecture, memory‑mapped bus interfaces, and IP integration flows
• Experience with Cadence tools and EDA flows
• Proven ability to define PPA goals, perform synthesis and static timing analysis
• Familiarity with DFT, gate-level simulations, and low-power design methodologies
• Comfortable with drafting specifications, design documents, and reviewing hardware/software integration requirements
• Have exposure to functional verification and writing or reviewing testbenches