SoC Architect

microTECH Global Limited; Netherlands; On-site; EUR 100,000 - 140,000; Full time

Job summary

microTECH Global Limited is seeking a skilled SoC Architect located in the Netherlands. The role demands significant experience in RTL design and strong collaboration with design teams. You will be integral in defining SoC architecture and ensuring successful chip implementation.

The ideal candidate will have over 12 years of experience in chip design, a strong understanding of hardware-software integration, and the ability to troubleshoot complex issues.

Qualifications

• Minimum of 12 years’ experience in RTL Design and CPU-based Chip Concepts.
• Experience with chip packaging and digital ASIC flows.
• Hands-on experience with IP selection and integration for SoC design.

Responsibilities

• Define the high-level architecture of the SoC.
• Collaborate with hardware teams for chip implementation.
• Coordinate with firmware teams for software execution efficiency.

Skills

RTL Design

ARM MCUs Subsystems

Digital ASIC Flows

Chip Packaging

Hardware-Software Interface Design

Troubleshooting Architectural Issues

Silicon Bring-Up

IP Integration

Low-Power Design Techniques

Signal Integrity Design

Job description

Job Title: SoC Architect

Location: The Netherlands

Job Type: Permanent

Salary: Range 100K – 140K Euros per annum

Role Overview

Looking for a SoC Architect. Someone who thrives in an environment where your proactive and can-do attitude is highly appreciated.

Key Responsibilities

• System Design & Integration: You will be responsible for defining the high-level architecture of the SoC, determining which components will be included on the chip.
• You will collaborate with the hardware design teams to guide the implementation of the chip's physical design.
• You will coordinate with our firmware & GNSS team to ensure the SoC Architecture supports efficient execution of software, including drivers, operating systems and applications.
• You will define and implement security features to protect the SoC from vulnerabilities.
• You will keep up with the advances in the semiconductor industry and make sure the SoC architecture remains scalable and adaptable for future generations of products.
• Managing product timelines and deliverables, making sure that the SoC Development follows the planned schedule and stays within budget.

Experience Required

• Minimum of 12 years’ experience in RTL Design, RTL Verification, CPU-based Chip/Components Concepts and Architecture.
• Deep understanding of ARM MCUs Subsystems, Memory Controllers, and memory architectures (e.g., SRAM, ROM, Flash, NVMe…).
• At least 10 years’ experience with the Digital ASIC Flows, RTL design, Design Verification, Debug and Trace methodologies, Test (e.g., DFT, JTAG, Scan, BIST).
• Solid understanding of chip packaging.
• Proficient in hardware-software interface design, including device drivers, firmware, and low-level software optimizations.
• Strong problem-solving skills to troubleshoot and resolve architectural issues related to SoC integration, performance, and power efficiency.
• Experienced with silicon bring-up, validation, and post-silicon debug methodologies.
• Practical experience with IP integration, including integration flows, interconnect design (e.g., AMBA, AXI, AHB), and managing key IP integration architecture tasks.
• Deep understanding of peripherals, Pin Function Assignment, and multiplexing, as well as familiarity with various communication protocols (e.g. MIPI, LVDS, SPI, I2C, UART).
• Experience in analog-digital interface design, including RF and Analog components like PLL, ADC, DAC, LNA, PA, DCDC, LDO… integration, and layout constraints for minimizing noise and signal interference.
• Knowledge of low-power design techniques, including clock gating, power gating, and multi-voltage domains (UPF/CPF).
• Deep understanding of library selection and design, with a focus on leakage power-aware methodologies to optimize performance and power trade-offs.
• Hands-on experience with IP selection to meet the specific needs of the design.
• Strong experience in selecting appropriate I/O technologies and designing for signal integrity, noise resilience, and power efficiency.
• Strong knowledge of pad ring placement and ESD strategy.
• In-depth expertise in clock and reset architecture design, including low-jitter clock distribution networks, clock domain crossing issues, and reset synchronization.
• Solid understanding of power management units and implementing various power sequencing schemes, including wake, sleep, and deep sleep modes for power efficiency.
• Solid Knowledge in signal processing, communication system.
• Exposure to all aspects of RFIC system design.