Senior Verification Engineer – Mixed-Signal & UVM Expert

IC Resources; Rijswijk; On-site; EUR 90,000 - 120,000; Full time

Job summary

IC Resources is seeking Senior Design Verification Engineers for a major US semiconductor manufacturer. You will shape the direction of cutting-edge IP for digital-AMS ASIC solutions and join a global team focused on designing and developing existing and new products.

The role demands strong UVM verification in mixed-signal environments, SystemVerilog expertise, and familiarity with real-number modelling.

Qualifications

• Expertise in UVM and SystemVerilog required.
• Experience in a mixed-signal environment.
• Proficiency in SystemVerilog and behavioural modelling of analog components for simulation within digital flows is highly desirable.
• Experience with real number modelling is highly desirable.

Responsibilities

• Shape the direction of cutting-edge IP for digital-AMS ASIC solutions.
• Design and develop existing and brand-new products as part of a global team.
• Contribute to verification strategies and methodologies across projects.

Skills

UVM

SystemVerilog

Mixed-signal environment

Behavioral modelling (analog)

Real number modelling

Job description

IC Resources is seeking Senior Design Verification Engineers for a major US semiconductor manufacturer. You will shape the direction of cutting-edge IP for digital-AMS ASIC solutions and join a global team focused on designing and developing existing and new products.

The role demands strong UVM verification in mixed-signal environments, SystemVerilog expertise, and familiarity with real-number modelling.