Senior MEMS Verification Engineer - UVM & SV Expert, Equity

Qabird; Rijswijk; On-site; EUR 65,000 - 85,000; Full time

Benefits offered by this job

Base salary

Bonus based on goals

Equity options

Job summary

Qabird is seeking a Senior Verification Engineer for their Rijswijk office. You will develop MEMS timing ICs, focusing on both analog and mixed-signal environments. Ideal candidates possess strong expertise in SystemVerilog, UVM methodologies, and have extensive experience in semiconductor verification.

The role includes developing verification plans, running simulations, and engaging with stakeholders to ensure efficient workflows.

Qualifications

• 5+ years of verification experience in the semiconductor industry.
• Proficient in verification using UVM.
• Strong experience writing SystemVerilog Assertions (SVA).

Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits.
• Develop UVM-based verification environment.
• Run simulations and debug results.

Skills

SystemVerilog

UVM

Scripting languages (Perl/Python)

Verilog

Analog schematic understanding

C++

Education

MS (BS) degree in electrical/computer engineering or related fields

Tools

Cadence Virtuoso

Job description

Qabird is seeking a Senior Verification Engineer for their Rijswijk office. You will develop MEMS timing ICs, focusing on both analog and mixed-signal environments. Ideal candidates possess strong expertise in SystemVerilog, UVM methodologies, and have extensive experience in semiconductor verification.

The role includes developing verification plans, running simulations, and engaging with stakeholders to ensure efficient workflows.