Verification Engineer II

The Preferred Supplier; Delft; On-site; EUR 70,000 - 90,000; Full time

Job summary

A leading supplier in technology is seeking an experienced ASIC Verification Engineer II for their Delft office. The role involves developing functional models for analog and mixed-signal circuits and performing full chip functional verification. Candidates should have a BA/BS in Electrical Engineering, experience with various circuit designs, and be skilled in Verilog/SystemVerilog. Excellent communication skills and the ability to work in a fast-paced team environment are essential. This position promises a unique opportunity in the heart of technology development.

Qualifications

• BA/BS Degree or higher in electrical engineering.
• Experience with analog and digital circuit design.
• Understanding of analog schematic and experience with Cadence Virtuoso.
• Experience with digital design languages, such as Verilog/SystemVerilog.
• Ability to learn new concepts and tools quickly.

Responsibilities

• Develop functional models for analog and mixed-signal circuits using Verilog.
• Write verification specifications based on required test cases.
• Develop test benches to verify the top level functions of full chips.
• Run verification test benches and communicate results to the team.

Skills

Analog circuit design

Digital circuit design

Verilog/SystemVerilog

Scripting languages (Perl/Python)

Python

Mixed-signal verification

Communication skills

Education

BA/BS Degree in Electrical Engineering

Tools

Cadence Virtuoso

Modelsim/Questasim

Job description

ASIC Verification Engineer II Delft, Netherlands

CMOS

Manager

X Corporation (Nasdaq: X), a market leader in MEMS timing, offers MEMS-based silicon timing system solutions. X's configurable solutions offer a rich feature set that enables customers to differentiate their products with high performance, small size, low power, and high reliability. With over 2 billion devices shipped to date, X is changing the timing industry.

Job Summary

Develop function models for analog and mixed-signal circuit and perform full chip functional verification.

Responsibilities

• Develop functional models for analog and mixed-signal circuits using Verilog or similar languages
• Write verification specifications based on required test cases
• Develop test benches in Verilog or similar languages/environments to verify the top level functions of full chips
• Run verification test benches and communicate results to the team for any fixes/improvements

Qualifications & Requirements

• BA/BS Degree or higher in electrical engineering
• Experience with analog and digital circuit design
• Understanding of Analog schematic and experience with Cadence Virtuoso
• Scripting languages such as Perl / Python
• Experience with digital design languages, such as Verilog/SystemVerilog

Desired Characteristics & Attributes

• Excellent written and verbal communication skills required
• Understanding of mixed signal designs verification flow (modelsim/questasim)
• Ability to learn new concept and tools quickly
• Ability to work well with others in a fast-paced collaborative team environment